Time split array logic element and method of operation

Details Time split array logic element and method of operation Time split array logic element and method of operation

1974-12-20

1976-10-19

Malzahn, David H.

Registers

Transfer mechanism

Traveling pawl

307207, 328 92, H03K 1920

Patent

active

039872866

ABSTRACT:
A standard logic array can be electrically altered at different time intervals to execute complex logic functions. Input variables to the array are processed in a network to generate sets of implicants of a complex function in one or more time periods. The implicants constituting the function are processed through a logic network or matrix as the logic personality of the matrix is altered. The implicant and logic networks may be personalized by (a) structure, (b) time signals, (c) personality signals, and (d) any combination of (a), (b) and (c). The standard array executes complex functions in a single time period or by processing one or more implicants in groups at different time periods. The testability of the array may be improved by appropriate interconnections of the array elements. The invention reduces the number of logic elements or part numbers a system designer must assemble to achieve desired objectives for a data processing machine. The arrays can be produced, stockpiled and structurally personalized at a later time as required by a system designer. The method of operating the array is compatible with data processing machine programming and operation.

REFERENCES:
patent: 3579119 (1971-05-01), Yau et al.
patent: 3731073 (1973-05-01), Moylan
patent: 3816725 (1974-06-01), Greer
patent: 3818252 (1974-06-01), Chiba et al.
D. Hutton & W. Kautz "A Simplified Summation Array for Cellular Logic Modules" IEEE Trans. on Computers Feb. 74 pp. 203-206.

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