Time slot multiplex system for the division multiplexing of digi

Multiplex communications – Wide area network – Packet switching

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370 68, H04J 302

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active

045120145

ABSTRACT:
A time slot multiplex device for a time division multiplex system having a voice memory for storing data words received on an input multiplex line, and a control memory for controlling the reading of said voice memory to an output multiplex line, incorporates logic circuitry for generating a plurality of associated pairs of addresses, one for said control memory and one for said voice memory, corresponding to a plurality of equally spaced time slots for a multi-channel connection to said output multiplex line of relatively high band width, in response to a single pair of associated addresses furnished by a higher ranking control means and a logic circuit which, in association with a time slot counter, generates the required addresses during cycling of the time slot counter through a single frame of the time division multiplex system.

REFERENCES:
patent: 3987251 (1976-10-01), Texier et al.
patent: 4068098 (1978-01-01), Thyselius
patent: 4071701 (1978-01-01), Leijonhufvud et al.
patent: 4168401 (1979-09-01), Molleron et al.
patent: 4258434 (1981-03-01), Glowinski et al.

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