Time shared programmable logic array

Details Time shared programmable logic array Time shared programmable logic array

1977-04-04

1978-04-11

Yusko, Donald J.

Communications: electrical

Digital comparator systems

340173AM, 307207, 364716, G11C 1140, H03K 1908

Patent

active

040841529

ABSTRACT:
This specification describes arrays for performing logic functions. In these arrays input variables are placed on a series of parallel input lines that intersect a number of parallel output lines in a grid of intersections. Field effect devices at these intersections have their gate terminals connected to one of the input lines and their source terminal connected to one of the output lines and through a load device to a source of potential. The drain terminals of these devices are either unconnected, connected directly to ground or connected to ground through one of two switching devices. The devices with unconnected drains are inoperative. The devices with their drains connected directly to ground are operative at all times. While the devices connected to ground through one of the switches are operative only when the switch is closed. The array can be time shared by two different logic functions by having one or the other of the switches off at any given time.

REFERENCES:
patent: 3895360 (1975-07-01), Cricchi et al.
patent: 3922647 (1975-11-01), Broeker, Jr.
patent: 3974366 (1976-08-01), Hebenstreit
patent: 3975623 (1976-08-01), Weinberger
patent: 4041459 (1977-08-01), Horninger

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