Patent
1996-09-27
1999-05-18
Ramirez, Ellis D.
395557, G06F17/00
Patent
active
059058692
ABSTRACT:
A multi-processor multi-node system having access to a low skew clock to synchronize processing events. This system uses a SCI network to distribute a low skew signal to synchronize the time of century clock counters on the different nodes. These counters are periodically synchronized with a signal from a selected master counter, so that all nodes will maintain approximately equal counter values. A single bit in a SCI header of send, echo, or idle packet is routed to all nodes via a SCI ring. Since the bit is inserted in existing packets, the creation of a special synchronizing packet is not required. Moreover, since the bit travels over existing lines, additional signal paths or extra wire are not needed.
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IEEE Standard for Scalable Coherent Interface (SCI), IEEE Std. 1596-1992 ISBN 1-55937-222-2; pp. 49-80, see specifically Section 3.4.6 "Global Time Synchronization".
Brewer Tony M.
Hornung Bryan D.
Hewlett-Packard Co.
Ramirez Ellis D.
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