Time multiplexing logic in physical design domain for...

Details Time multiplexing logic in physical design domain for... Time multiplexing logic in physical design domain for...

2006-08-22

2010-06-29

Phan, Tri H (Department: 2471)

Multiplex communications

Data flow congestion prevention or control

Flow control of data transmission through a network

C370S391000, C370S532000, C370S538000, C326S038000

Reexamination Certificate

active

07746785

ABSTRACT:
An apparatus and method are provided to perform a time multiplexing logic in a module, are provided including identifying a driving flop and a receiving flop in the module, receiving a modified input signal, and identifying a worst case timing path for the modified input signal to transmit from the driving flop to the receiving flop. The time multiplexing logic of the apparatus and method further identifies a predetermined point of the worst case timing path, and inserts a logic unit at the predetermined point allowing the time multiplexing logic circuit to process and output the modified input signal at a maximum frequency.

REFERENCES:
patent: 5646545 (1997-07-01), Trimberger et al.
patent: 5761483 (1998-06-01), Trimberger
patent: 6480954 (2002-11-01), Trimberger et al.
patent: 7016354 (2006-03-01), Vangal et al.
patent: 7330924 (2008-02-01), Kao et al.
patent: 2008/0013457 (2008-01-01), Berman et al.

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