Time jitter determining apparatus

Details Time jitter determining apparatus Time jitter determining apparatus

1979-10-29

1982-09-21

Thesz, Joseph M.

Registers

Platform operated

Platform actuated traffic counters

235 92SH, 328163, 360 51, G06M 308

Patent

active

043508790

ABSTRACT:
The jitter determining apparatus uses only a jittery clock signal of period T.sub.b recovered from the received data signal to determine peak to peak jitter J.sub.pp and jitter distribution. The apparatus includes an AND gate having a pair of inputs. The inputs are coupled to a first signal which is the jittery clock signal delayed by a fixed amount nT.sub.b where n is preferably greater than 5, and to a second signal which is a jittery pulse signal generated from the jittery clock signal. The second signal is also controllably delayed by a factor greater than twice the jitter J.sub.pp. The AND gate produces output pulses when coincidence occurs between the two signals as the delay of the second signal is selectively varied. A counter counts the pulses for each selected delay position and thus provides the peak to peak time jitter J.sub.pp of the clock signal.

REFERENCES:
patent: 3382492 (1968-05-01), Santana
patent: 3395399 (1968-07-01), Goodenow
patent: 3548175 (1970-12-01), Tomlin
patent: 3643170 (1972-02-01), Stanger
patent: 3711773 (1973-01-01), Hekimian et al.
patent: 3725796 (1973-04-01), Schenk et al.
patent: 3895186 (1975-07-01), Yoshida et al.
patent: 3916307 (1975-10-01), Hekimian
patent: 3938182 (1976-02-01), McKenna
patent: 3947673 (1976-03-01), Jordan et al.
"Single RC Network Gives Variable Delay, Preserves Input-Signal Pulse Width", Electronic Design, Jan. 4, 1979, p. 168.

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