Pulse or digital communications – Receivers – Automatic gain control
Reexamination Certificate
1999-11-19
2002-12-17
Vo, Don N. (Department: 2631)
Pulse or digital communications
Receivers
Automatic gain control
C375S350000
Reexamination Certificate
active
06496550
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to data acquisition and digital data processing systems, and, more particularly, to read channels of data stored in a mass memory device.
BACKGROUND OF THE INVENTION
In recent years the mass storage memory market has gone through an enormous growth, especially in the area of magnetic disks. The continuous demand for higher memory capacity and for a higher data processing speed has prompted manufacturers to invest more resources in a highly competitive and rapidly evolving market.
The introduction of digital processing on signals originating from the read pick-ups has produced a significant increase in the linear storage density. For example, the techniques of storing data on magnetic supports, e.g., a magnetic disk, are based on the ability of ferromagnetic materials to remain biased in the direction of the applied magnetic field, even when the magnetic field is no longer applied. The data are stored by either inverting or not inverting the direction of magnetization on the disk. During a read phase, the presence or absence at a certain instant of a transition in the magnetic flux reveals the data sequence.
For the same magnetic support properties, the distance between two adjacent transitions must be reduced to increase the linear storage density. Eventually, an intersymbol interference (ISI) becomes unavoidable. The problem of a correct detection of symbols affected by ISI and by noise is not limited to magnetic disks. This problem may also arise in similar mass memory supports. Generally, it represents the main problem in data transfer channels, of which the read channels of hard disks drives (HDD) represent just one important example.
The efforts to overcome the problem of ISI have led to the development and use of special coding techniques, such as Partial Response (PR) signaling. These coding techniques are based on the fact that if the ISI on the transmitted data is known, then it can be taken into consideration during reception so that the correct sequence of the original data can be reliably reconstructed.
By sampling the signal originating from a read pick-up with a clock synchronous with the writing clock, it is possible by the use of special algorithms of maximum likelihood (ML) to obtain the most likely data sequence effectively read from the memory support. By combining the PR technique with ML methods, PRML systems are implemented. The PRML decoding techniques work on a sequence of samples and the algorithms are digitally implemented.
The electronics of a read/write channel must ensure a high speed. For some functions, such as clock generation, for example, it is also necessary to have a very high accuracy. The variety of necessary circuits include analog and digital filters, A/D converters and low jitter voltage controlled oscillators (VCO) being among the most significant. Moreover, during a read phase, it is necessary to interface with the reading heads using low noise wide band amplifiers. During a write phase, the writing head must be driven with a relatively high current for a magnetic support.
Currently, a read/write channel with a relatively standard architecture has not yet been established. Various approaches have been proposed to meet the requirement of a higher speed and higher storage density. These approaches range from a completely analog approach to a completely digital approach.
The electronics of a HDD or similar apparatus requires both analog and digital functionality. Manufacturing reasons, such as the standardization of the design and the adaptability among different technologies, foster implementation in the digital domain of functions that historically were implemented with analog circuits. Commonly, the analog part is dedicated to the correct generation of timing signals for writing and reading, and for interfacing with the heads, e.g., Pre-Amp, VGA, MRA, LPF, OFFSET-STAGE, ATOD, VCO, etc., as shown in FIG.
1
. The digital part is dedicated to the processing of data and for communicating with a data bus of the system, e.g., digital filters, maximum-likelihood detector, encoder-decoder, etc.
By way of example, a typical functional scheme of a single stream HDD read channel with digital processing of data is depicted in FIG.
1
. As shown in the example of
FIG. 1
, read channels include automatic gain control circuits (AGC) implemented with a variable gain amplifier. The amplifier is controlled by a dedicated digital-to-analog converter DAC_VGA. The converter is controlled by the digital processing circuitry downstream of the analog/digital switch (ATOD) to maintain constant the amplitude of the signal fed to the converter's input.
In case of a magnetic support, such as in a HDD, the Magnetic Resistive Asymmetry (MRA) block eliminates or attenuates the second harmonic, i.e., contribution of the term a*x
2
, of the input analog signal originating from the read head MR. Even this corrective operation of the signal spectrum is dynamically controlled through a dedicated digital-to-analog converter DAC_MRA. The equalization of the signal is performed by the low pass filter LPF that controls the cut-off frequency through the DAC_FC converter, and the boost through the DAC_BOOST converter. These converters convert analog control signals of the transfer function of the low pass filter LPF via digital commands, e.g., Word_FC and Word_Boost.
In cascade to the equalization low pass filter LPF, an OFFSET STAGE compensates the offset of the digital-to-analog converter present in the ATOD block. Even in this case, there is a control loop for compensating the offset implemented by the DIGITAL POST PROCESSING block and the DAC_OFF converter. Moreover, the DIGITAL POST PROCESSING block maintains a correct sampling synchronized by the ATOD block. The control is implemented by the DAC converter, and the voltage controlled oscillator VCO.
The above described system has several drawbacks. First, the digital data processing after the conversion takes place at full-rate, thus limiting the maximum frequency that the system may reach for a certain available technology. Second, the ATOD block operates at full-rate and represents a real bottleneck for the entire architecture in terms of the maximum possible frequency, current consumption and noise generated in the analog portion.
SUMMARY OF THE INVENTION
A significant enhancement of the performance of a read channel may be obtained by using two distinct offset compensating circuits for the two ATOD converters. A single path is implemented parallel to a time interleaved converter. Each path is independently controlled by the post-processing circuit via a respective digital-to-analog converter.
The appearance of spurious patterns in the frequency domain are prevented by duplicating the compensation elements and by controlling them independently from each other. These signals originate from offset mismatches which are likely to occur between the digital-to-analog converter of the ATOD converter of the signal path for the even bits, and that of the digital-to-analog converter of the ATOD converter of the signal path for the odd bits.
In particular, generation of uncorrelated patterns in the signal spectrum, which would degrade the performance of the entire read channel, are prevented. The converter, in a typical application as that of a modern HDD, works above the Nyquist frequency. These patterns are typically formed by lines in correspondence of multiples of Fs/2.
REFERENCES:
patent: 6028727 (2000-02-01), Vishakhadatta et al.
patent: 6219387 (2001-04-01), Glover
patent: 6292912 (2001-09-01), Cloke et al.
Alini et al.: “A 200-Msample/s Trellis-Coded PRML Read/Write Channel with Analog Adaptive Equalizer and Digital Servo” IEEE Journal of Solid-State Circuits, vol. 32, No. 11, Nov. 1997, pp. 1824-1838, XP000752893 *p. 1824, column 1, line—p. 1835, column 1, line 13.
R. Khoini-Poorfard and J.A. Johns: “Mismatch Effects in Time-Interleaved Oversampling Converters”, IEEE International Symposium on Circuits and Systems (ISCAS), Linear Circuits and Systems (LCS),
Bruccoleri Melchiorre
Demicheli Marco
Ottini Daniele
Savo Alessandro
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Jorgenson Lisa K.
STMicroelectronics S.r.l.
Vo Don N.
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