Multiplex communications – Wide area network – Packet switching
Patent
1984-06-06
1986-01-14
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
370 67, H04Q 1104
Patent
active
045649367
ABSTRACT:
An equipment for interchanging time slots of time division multiplex signals on a plurality of highways. Data bit signals in respective time slots incoming on respective highways are one-bit delayed at one after another of the highways by shift registers of different stages and are converted into parallel data at respective serial-parallel converters. The parallel data of respective time slots are read out from the converters sequentially and are stored in different addresses in a speech memory over the entire frame of each highway in response to the sequential clock pulses. The data stored in the speech memory are read out at every intervals of adjacent clock pulses and are distributed to respective parallel-serial converters connected to different highways in response to the time intervals of the clock pulses. The addresses of the speech memory to be accessed in the read-out operations are obtained from an address control memory in which the address data are written by a central control unit. Thus, a desired time slot interchange is performed according to the address data stored in the address control memory and the data signals interchanged are transmitted onto output highways. Shift registers are used for matching time slots on output highways.
REFERENCES:
patent: 3466397 (1969-09-01), Benowitz et al.
patent: 3673336 (1972-06-01), Thomas
patent: 3881064 (1975-04-01), Schlichte
patent: 3996566 (1976-12-01), Moran
patent: 4138597 (1979-02-01), Ashford
Nitsuko Limited
Olms Douglas W.
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