Time division switching circuit with time slot interchange

Details Time division switching circuit with time slot interchange Time division switching circuit with time slot interchange

1979-10-01

1982-08-10

Stewart, David L.

Multiplex communications

Wide area network

Packet switching

370 59, 370 63, 370 64, 370 66, H04Q 1104

Patent

active

043441700

ABSTRACT:
A time division switching circuit with time slot interchange uses an input shift register to convert one-frame binary coded input data of time division multiplex type from an incoming line into a parallel bit output. The parallel bit output undergoes gate control of a gate matrix and its bit array is statically changed to a given bit array. The on/off control of the gate at the cross point of the gate matrix is conducted according to parallel bit outputs of a plurality of control shift registers which stores predetermined contents. The one-frame bit data thus exchanged are supplied to an output shift register. They are transmitted to an outgoing line as binary coded output data of time division multiplex type.

REFERENCES:
patent: 3217106 (1965-11-01), Muroga
patent: 3236951 (1966-02-01), Yamamoto
patent: 3706853 (1972-12-01), Saito
patent: 3812294 (1974-05-01), Pederson
patent: 4154986 (1979-05-01), Howells

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