Time-division multiplexer with reduced delay time

Details Time-division multiplexer with reduced delay time Time-division multiplexer with reduced delay time

1994-12-12

1996-05-28

Safourek, Benedict V.

Multiplex communications

Wide area network

Packet switching

3701001, 370112, H04J 302

Patent

active

055219209

ABSTRACT:
A multiplexer having the capability of multiplexing/demultiplexing data with reduced delay caused by exchanging data. The time-division multiplexer of the invention includes a plurality of time-slot-conversion memories which can write/read the data consisting of specific multi-frames with a specific frame unit, a write-timing pulse generator which generates write/read timing to a multi-frame alignment memory with a specific frame unit. The multiplexer transmits/receives the data to/from the transmission interface or the terminal interface with the specific frame unit. Another kind of multiplexer of the invention includes a distributed time-slot-conversion memory which can write/read the data with a specific frame unit and a selector. The multiplexer transmits/receives the data to/from the transmission interface, the terminal interface, the transmission line, or the terminal with a specific frame unit.

REFERENCES:
patent: 4941141 (1990-07-01), Hayano
patent: 4999832 (1991-03-01), Chen et al.
patent: 5123012 (1992-06-01), Suzuki et al.
patent: 5257260 (1993-10-01), Breidenstein et al.
patent: 5331632 (1994-07-01), Aaron et al.

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