Time division multiplexer/demultiplexer with deterministic time

Details Time division multiplexer/demultiplexer with deterministic time Time division multiplexer/demultiplexer with deterministic time

1989-02-21

1990-05-22

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 951, H04J 316

Patent

active

049282735

ABSTRACT:
A frame building procedure for use in time division multiplexer systems for building a frame with N slots numbered #1, #2, #3, . . . #N in increasing time order. A slot assignment sequence is generated in successive iterations I by initially assigning slot #1 as the first assignment in the sequence. N/2.sup.I is added to the slot numbers of all previously assigned slots during each iteration. Additionally, during each iteration, I is incremented by unity. The iterations are performed until all N slots are assigned when N/2.sup.I =1.

REFERENCES:
patent: 3982074 (1976-09-01), Clark
patent: 4071701 (1978-01-01), Leijonhufund et al.
patent: 4763319 (1988-08-01), Rozenblit

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