(Time division multiplex) switching system for routing trains of

Details (Time division multiplex) switching system for routing trains of (Time division multiplex) switching system for routing trains of

1983-12-12

1986-07-29

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 94, H04Q 1104, H04J 324

Patent

active

046034161

ABSTRACT:
The system switches data packets, with headers, from input junctions to output junctions. The series incoming packets are converted into parallel packets. The headers of each incoming packet and the identity of the involved input junction are transferred to the address inputs of a control memory. The control memory supplies a new header which is assigned to the incoming packet, in replacement of the original header, in order to form the parallel outgoing packet with the remaining part of the incoming packet. A buffer memory is cyclically enabled for writing, in order to store the outgoing packets. Each parallel packet read out of the buffer memory is converted into a series packet. Queues store the addresses of a packet in the buffer memory, and are selectively enabled for writing, depending on information from the control memory. Each queue is assigned to an output junction. Responsive to a signal for indicating that one of the output junctions is enabled, the address contained in the corresponding queue is read, in order to find the output packet which is to be transferred to the outgoing junction in the buffer memory.

REFERENCES:
patent: 4168400 (1979-09-01), de Couasnon et al.
patent: 4271506 (1981-06-01), Broc et al.
patent: 4314233 (1982-02-01), Clark
patent: 4354263 (1982-10-01), Bordry et al.
patent: 4375097 (1983-02-01), Vlug
patent: 4451827 (1984-05-01), Kahn et al.
patent: 4464749 (1984-08-01), Vlug

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