Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
1998-07-08
2002-10-22
Ton, Dang (Department: 2731)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C370S370000, C370S372000, C370S375000, C370S380000
Reexamination Certificate
active
06470011
ABSTRACT:
BACKGROUNDS OF THE INVENTION
1. Field of the Invention
The present invention relates to a control system and a control method of a time sharing switch in an electronic switching system, and more particularly, to a time division multiplex highway switch control system and control method of T-S-T three-stage switches in a multiprocessor typed electronic switching system.
2. Description of the Related Art
Generally, there has been used a conventional method of providing a multiprocessor typed electronic switching system with each processor for every predetermined number of accommodating terminals, for the purpose of dispersing the load. When forming a switch of a large volume by use of such a multiprocessor typed electronic switching system, there has been adopted a method of forming a general time sharing switch having a T-S-T three-stage structure, with a plurality of dispersedly provided first T-stages and third T-stages respectively controlled by a plurality of corresponding processors dispersedly provided and with second S-stages centrally controlled by a single processor.
This kind of electronic switching system is disclosed in, for example, Japanese Patent Publication Laid-Open (Kokai) No. Showa 61-58397, “Time Sharing Communication Channel Control Device”. The structure of the conventional general time sharing switch disclosed in the same publication is shown in FIG.
10
.
With reference to
FIG. 10
, the conventional T-S-T three-stage time sharing switch system comprises first switches
11
,
12
to
1
n
, second switches
21
,
22
to
2
n
, third switches
31
,
32
to
3
n
, processors
41
,
42
to
4
n
for controlling the first switches and the third switches, a processor
40
for controlling the second switches
21
,
22
to
2
n
, an interposing bus
60
between processors for connecting the processors
40
,
41
,
42
to
4
n
with each other, output highways
71
,
72
to
7
n
for connecting the respective first switches
11
,
12
to
1
n
with all the second switches
21
,
22
to
2
n
, output highways
81
,
82
to
8
n
for connecting the respective second switches
21
,
22
to
2
n
with the corresponding third switches
31
,
32
to
3
n
and a memory
90
storing the spare time slot information of the respective second switches
21
,
22
to
2
n
which are referred to by the processor
40
in order to control the second switches
21
,
22
to
2
n.
Considering the case of achieving a switching connection from a terminal
102
under the control of the processor
42
to a terminal
101
under the control of the processor
41
, it is necessary to connect a path passing from the terminal
102
to the terminal
101
via the first switch
12
, the second switch
21
, and the third switch
31
, in this connection. In order to enable the second switch to exchange output highways, it is necessary to coincide the time slots on the output side of the first switch and the time slots on the input side of the third switch.
Therefore, the processor
42
on the input side of this connection asks the processor
40
about the spare time slots available for the connection to the third switch
31
accommodating the terminal
101
of the connection party, through the interposing bus
60
between processors. The processor
40
makes a comparison between the spare time slots of the output highway
72
of the first switch
12
used for the connection and the spare time slots of the output highway
81
of the second switch
12
, and selects each time slot of being both empty, thereby performing the connection of the corresponding highway. The processor
40
notifies the processor
42
of the selected time slot number “m”. The processor
42
interconnects the time slots for accommodating the terminal
101
and the time slots “m” in the first switch
12
. The processor
42
asks the processor
41
to connect to terminal
101
by use of the time slots “m” through the interposing bus
60
between processors. The processor
41
interconnects the time slots for accommodating the terminal
102
and the time slots “m”, in the third switch
31
. As a result, the connection from the terminal
101
to the terminal
102
is completed.
However, in the above-mentioned conventional highway switch control method, a single processor controls highways. Therefore, when a fault occurs in this processor, the whole system fails to do switching, even if there is no fault in a processor controlling T-stage.
In the above publication, disclosed is an electronic switching system of a redundant structure including a plurality of dispersedly provided time sharing switches and thereby capable of eliminating the fault affecting the whole electronic switching system even if a fault occurs in a common control portion. However, since the ratio of the redundant structure portion in the electronic switching system is increased, this invention is not suitable for a large scaled switching system such as the T-S-T structure.
SUMMARY OF THE INVENTION
An object of the present invention is, in order to solve the above problems, to provide an extremely reliable highway switch control system and control method suitable for decentralized control, with commonly controlled portion eliminated from the T-S-T three-stage time sharing switch system.
Another object of the present invention is, in addition to the above object, to provide a highway switch control system and control method suitable for a large-scaled switching structure like a T-S-T structure without redundant circuitry.
According to the first aspect of the invention, a highway switch control system for controlling a time division multiplex highway switch of T-S-T three-stage switches in a multiprocessor typed electronic switching system, comprises
a plurality of sets of first switches of time sharing switching method, second switches of highway switching method, third switches of time sharing switching method, and control means for controlling each switch,
interconnecting means for interconnecting the control means each other in each set,
first output highways for connecting each of the first switches in every set to all the second switches of all sets, and
second output highways for respectively connecting the second switches to the third switches in every set,
two of the control means to be connected together getting information on spare time slots of the mutual switches through the interconnecting means and deciding time slots for use in the connection, thereby controlling a connection between required switches.
In the preferred construction, the highway control system further comprises connection means for exclusive use in connecting the control means to the second switches in each set.
In the preferred construction, the respective sets further comprise storing means for storing information on spare time slots in the respective switches, and the control means decide time slots for use in a connection with reference to the information stored in the storing means.
In another preferred construction, the respective sets further comprise storing means for storing information on spare time slots in the respective switches, and the control means makes a comparison between the information stored in the storing means of one's own and the information stored in the storing means of the connected party, so to detect the coincident spare time slots, which are defined as the time slots for use in the connection.
According to the second aspect of the invention, a highway switch control method for controlling a time division multiplex highway switch by control means provided correspondingly to first switches of time sharing switching method, second switches of highway switching method, and third switches of time sharing switching method forming T-S-T three-stage switches, in a multiprocessor types electronic switching system, the method comprising the steps of
a step of deciding time slots for use in this connection by examining spare time slots of the first switch and the third switch, when connection the first switch to the third switch, and
a step of connecting a
Moride Hiroyuki
Tanimura Takuji
Foley & Lardner
Sam Phirin
Ton Dang
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