Pulse or digital communications – Equalizers – Automatic
Reexamination Certificate
1998-05-07
2001-12-18
Chin, Stephen (Department: 2634)
Pulse or digital communications
Equalizers
Automatic
C333S018000, C708S323000
Reexamination Certificate
active
06332000
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an equalizer used in a high-speed communication, and more particularly to a time division equalizer capable of decreasing the number of multipliers.
2. Description of the Related Art
Recently, with the remarkable development in hardware and software techniques and user's demands for high-quality and high-speed which may be incorporated in a multi-functional communication system, the information service field has been dramatically innovated. In this information service field, the real-time data transmission with a high quality may be essential to the communication techniques.
The communication system may be divided into the wire communication and the wireless communication. However, both these communications contain distortions such as a multinterference and a white noise. In the case where the channel distortion is very poor, the reliability of data demodulated at a receiving terminal is debased so that the signal-to-noise rate is deteriorated. As a result, it is impossible to provide a good quality of communication service for users. Accordingly, for removing the noise signals other than the object signal, most modems contain an adaptive equalizer, which makes an pre-estimate of the time-variant channel characteristics.
For example, the adaptive equalizer has been used in a receiver of the VSB (Vestigial Side Band) modem which is based on the ground broadcast of the ATV (Advanced TV) in America. The multipliers corresponding to the number of tabs are needed in not only an adaptive filter used in such an adaptive equalizer but also the high-speed filter. In the case where the filter is implemented with hardware, there is a problem on its large size. Further, in the case where the filter is an adaptive filter in the blind equalizing mode in which the tab coefficient is updated for one sampling period, the adaptive filter needs multipliers twice as many as those in other modes.
FIG. 1
is a circuit diagram illustrating a conventional equalizer. As shown in
FIG. 1
, the conventional equalizer includes a delaying part
11
, a coefficient updating parts
12
, a convolutional operating part
13
, a feed-back filtering part
14
and an error value generating part
15
. The delaying part
11
includes a plurality of flip-flops coupled in series to one another, delaying input data for a predetermined time in response to a symbol signal. Each of the coefficient updating parts
12
receives the delayed data and the previous error value and then updates the coefficient. The convolutional operating part
13
multiplies each updated coefficient by the delayed data using a plurality of multipliers, and sums up the outputs of the multipliers. The feed-back filtering part
14
is coupled between the adder in the convolutional operating part
13
and the output terminal of the equalizer, for filtering the output of the adder. The error value generating part
15
coupled between the output terminal of the equalizer and the coefficient updating parts
12
calculates the error value of the equalizer.
Referring again to
FIG. 1
, the convolutional operating part
13
has N multipliers and the coefficient updating parts
12
has N multipliers so that the adaptive equalizer are in need of 2N multipliers. Accordingly, when such a conventional equalizer is fabricated on a single semiconductor chip, a large area is required.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide an equalizer occupying small chip size, by decreasing the number of multipliers using a time division mode.
Another object of the present invention is to provide equalizer which can be implemented by a small number of tabs of the filter with the reduction of its manufacturing cost.
In accordance with an aspect of the present invention, there is provided an adaptive equalizer comprising: a plurality of first delaying means for delaying input data in response to a symbol clock signal; a clock generating means for producing a plurality of control signals using a system clock signal which is faster than a symbol clock signal, for classifying the delayed data; a plurality of selecting means for selecting output data from the first delaying means in response to the control signals provided by the clock generating means; a plurality of coefficient value updating means for receiving a previous error value and alternatively receiving the delayed and selected input data and then updating a coefficient value; a convolutional operating means for receiving outputs of the coefficient value updating means and alternatively receiving the delayed and selected input data; and an error value generating means for calculating an error value from an output of the convolutional operating means and providing the calculated error to the plurality of coefficient value updating means.
In accordance with another aspect of the present invention, there is provided an adaptive equalizer including a plurality of delaying means for delaying input data in response to a symbol clock signal, a plurality of coefficient value updating means, a convolutional operating means and an error value generating means, the adaptive equalizer comprising: a plurality of selecting means for selecting output data from the first delaying means in response to the control signals; and a clock generating means for producing, in time division mode, the control signals using a system clock signal which is faster than a symbol clock signal, for classifying the delayed data, wherein the control signals are out of phase;
REFERENCES:
patent: 3814917 (1974-06-01), Nussbaumer
patent: 3868603 (1975-02-01), Guidoux
patent: 5285474 (1994-02-01), Chow et al.
patent: 5359624 (1994-10-01), Lee et al.
patent: 5450339 (1995-09-01), Chester et al.
patent: 5579340 (1996-11-01), Tokuriki et al.
patent: 5642382 (1997-06-01), Juan
patent: 6209014 (2001-03-01), Prasad
Blakely & Sokoloff, Taylor & Zafman
Chin Stephen
Fan Chieh M.
Hyundai Electronics Industries Co,. Ltd.
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