Time dependent master reset

Details Time dependent master reset Time dependent master reset

1979-05-09

1981-05-05

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307296R, 361 89, 361110, 361187, H02H 720, H02H 3093, H02H 3247

Patent

active

042661455

ABSTRACT:
A circuit for use with logic circuitry preventing any transients due to the power down and power up conditions of a power supply from causing any false or random operations of the logic. The turn off transients are suppressed by a reset signal to the logic circuitry generated by a timing module which is triggered when it detects an absence of AC signal over a specified period of time and is then held in a reset mode until the power supply voltage completely decays. The turn on transients are suppressed by a reset signal to the logic circuitry generated by the timing module, which is held in a reset mode until the power supply voltage has stabilized.

REFERENCES:
patent: 3725675 (1973-04-01), Olsen
patent: 4099068 (1978-07-01), Kobayashi et al.
patent: 4122359 (1978-10-01), Breikss
patent: 4151425 (1979-04-01), Cappa

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