Time delay control for serial digital video interface audio rece

Dynamic magnetic information storage or retrieval – Recording for changing duration – frequency or redundant...

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360 191, 360 331, 360 362, 365221, 358343, G11B 500, G11B 502

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053232720

ABSTRACT:
An audio receiver FIFO memory buffer in the serial digital video interface allows improved timing synchronization between video and audio information. Furthermore, it eliminates unpleasant sound effects when multiple data samples are skipped or repeated in series. This FIFO receiver buffer receives data at an input write-data rate filling up the memory storage cells therein. An output read-data signal clocks the data out of the memory storage cells. The FIFO's fullness is monitored and maintained, in response to an external signal, to within a specified range delimited by an upper and a lower threshold. If the FIFO buffer fullness is below the range's lower threshold, then the FIFO's read address pointer is held so that the immediately preceding read out data element is read out again, but only once. On the other hand, the FIFO buffer fullness is over the range's upper limit, then the FIFO's write address pointer is held so that the immediately preceding written in data element is written over, but only once.

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Patent Abstracts of Japan vol. 6, No. 145 (P-132) Aug. 4, 1982 & JP-A-57 066 515 (Victor Co of Japan).
International Radio Consultative Committee Recommendation 656 International Radio Consultative Committee Recommendation 601-2.
Proposed Society of Motion Picture and Television Engineers Standard 125M Audio Engineering Society Recommended Practice AES3-1985(ANSI S4.40-1985).

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