Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2001-12-26
2003-09-30
Vanderpuye, Kenneth (Department: 2661)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S389000
Reexamination Certificate
active
06628658
ABSTRACT:
CLAIM FOR PRIORITY
This application claims priority to International Application No. PCT/DE00/00392 which was published in the German Language on Aug. 31, 2000.
TECHNICAL FIELD OF THE INVENTION
The invention relates to a method and a circuit arrangement for the time-critical routing of data to a clocked interface with asynchronous data transmission.
BACKGROUND OF THE INVENTION
In existing and future communication, systems, in particular communications systems operating according to the asynchronous transfer mode (ATM), data is and will be transmitted in a cell stream formed from cells or IP (Internet Protocol) packets. Specifically in the case of communications systems which operate according to the asynchronous transfer mode, the ATM layer model is used for functionally dividing the communications tasks, the ATM layer model being composed, like the OSI (Open Systems Interconnection) reference model from a plurality of communications layers which are independent of one another. These include the physical layer, the ATM layer, the ATM adaptation layer (AAL) and the user-oriented layers designated as “higher layers” in the OSI terminology. The function of a layer is to make available services for the next higher layer. In particular, the physical layer makes available a transmission interface for the cells of the superordinate ATM layer. This interface has been defined by the ATM forum as a uniform, clocked interface between the physical layer and the higher layers of communications devices which operate according to the asynchronous transfer mode, the interface being known in the specialist field by the name “Universal Test and Operation PHY-interface for ATM” or “Utopia” for short—see in particular ATM Forum, Level 2, v1.0, June 1995, pages 8-15 and 21-24.
In this UTOPIA Level 2 interface which is standardized by the ATM Forum, during the routing of the data to the interface very critical signaling occurs which gives rise to a number of technical implementation problems, particularly in the upstream direction, i.e. from the physical interface—also referred to as secondary side—to the communications system—also called primary side. Inter alia, the UTOPIA specification requires, for example, setup times of at least 4 nsec for a 50 MHz UTOPIA interface and hold times of at least 1 nsec. Owing to these setup and hold time requirements, all the signaling signals must be sampled at the input end immediately in order to be able to initiate the reaction to the signaling signals in the subsequent clock period, i.e. the signaling between the primary side and the secondary side is very time-critical. Furthermore, the standardized UTOPIA Level 2 interface standardizes a plurality of different complex signaling operations, the processing of which requires a complex control logic owing to their number. The implementation of such rapid reaction times and the implementation of the required complex control logic requires suitable hardware support, i.e. high speed logic modules such as ASICs (Application Specific Integrated Circuit) or high speed, small FPGAs (Field Programmable Gate Array) with short, internal signal transit times.
In the case of the standardized UTOPIA Level 2 interface, in particular the “Multiphysical” UTOPIA Level 2, there is additionally provision for a plurality of physical interfaces to be connected to the ATM layer, which requires address decoding and control with respect to the physical layer which is to be addressed. Furthermore, the previously described complexity of the different signaling operations in the case of a “multiphysical” operation of the UTOPIA interface is considerably increased, i.e. a complex and time-critical routing and decoding logic is necessary for the time-critical routing of data from a plurality of physical layers to the one ATM layer owing to the large number of different complex signaling operations and the selection of the physical layer which is authorized to transmit data in each case.
SUMMARY OF THE INVENTION
The invention relates to a method and a circuit arrangement for the time-critical routing of data to a clocked interface with asynchronous data transmission, there being parallel transmission of data between a physical layer, or at least one physical layer, and a further layer in accordance with a standardized layer model, of a ready signal which is generated by the physical layer and which indicates or does not indicate a data transmission request, and of a release/blocking signal which is generated by the further layer in order to route the data transmission and/or if appropriate of a plurality of address signals which are generated by the further layer. In addition, a reaction to a change in the release/blocking signal or in the ready signal occurs within at least one clock period.
In one embodiment of the invention, there is time-critical routing of the data to a clocked interface with asynchronous data transmission, in particular the interface between a physical layer, or between a plurality of physical layers, and the ATM layer.
In one aspect of the invention, the release/blocking signal is indicated to the physical layer delayed by one clock period, and the data to be transmitted in parallel is routed a priori to the clocked interface by the physical layer, and a reload signal for routing the data to the interface in a suitably timed and clocked fashion is generated by a logic connection of the delayed release/blocking signal and of the ready signal which is generated by the physical layer. The delaying of the release/blocking signal which is generated by the further layer and the subsequent logic connection of the delayed release/blocking signal to the ready signal which is generated by the physical layer enables very short reaction times to be obtained in different signaling operations. As a result, the number of the signaling scenarios or cases standardized by the ATM Forum is reduced to one case, i.e. the different time-critical signaling operations which occur during the operation of the interface are processed by the method according to the invention using a single, simple control logic. This means that no additional cost-intensive, high speed logic modules such as FPGAs for implementing a complex control logic are necessary to implement the method according to the invention but instead simple standard logic modules such as gates and flipflops can be used. In particular, the signaling requirements of future UTOPIA standards which are already in planning, for example UTOPIA Level 3 —see ATM Forum PHY WG, UTOPIA Level 3 Baseline Text, December 1998—with maximum clock rates of virtually 104 MHz and data bus widths of 32 bits can be advantageously realized using the method according to the invention, especially since in the field it is considered impractical to realize a complex control logic which is necessary to implement the UTOPIA Level 2 and 3 Standard without the method according to the invention with logic functions which are currently available in ASICs or high speed, small FPGAs owing to the extremely short signal transit times which are required.
According to another embodiment of the invention, when there is a reload signal which indicates a data transmission, further data is routed to the interface, and when there is a reload signal which indicates no data transmission, the currently present data and no further data is routed to the interface. As a result, data is routed to the interface in a particularly advantageous way after the transmission of the currently present data by the delayed release or blocking signal has already taken place, i.e. further data is routed to the interface immediately after the transmission of the currently present data. In addition, this ensures that no data can be reloaded from the physical layer to the clocked interface without a ready signal which indicates a data request or a reload signal which indicates a data release.
The logic connection of the delayed release/blocking signal and of the ready signal generated by the decentralized device is advantageously carried out accordi
Morrison & Foerster / LLP
Siemens Aktiengesellschaft
Vanderpuye Kenneth
LandOfFree
Time-critical control of data to a sequentially controlled... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Time-critical control of data to a sequentially controlled..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Time-critical control of data to a sequentially controlled... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3107220