Tiling in picture memory mapping to minimize memory bandwidth in

Details Tiling in picture memory mapping to minimize memory bandwidth in Tiling in picture memory mapping to minimize memory bandwidth in

1997-11-18

2000-08-15

Chauhan, Ulka J.

Computer graphics processing and selective visual display system

Computer graphic processing system

Integrated circuit

345203, 348717, G06F 1576

Patent

active

061044164

ABSTRACT:
A method of storing a picture in a memory such that the latency of the memory can be reduced when retrieving a picture from the memory to be displayed while still reducing the bandwidth when retrieving an array portion of the picture from the memory, and a memory architecture. The memory is subdivided into a plurality of words for storing a picture having rows and columns. The picture is partitioned into one or more tiles each having a predetermined number of rows and columns. The number of bytes in one row of one tile is equal to the number of bytes in one word, for storing the data in one row of a tile in one word. The chrominance Cr and Cb components can be stored in one word, with the first 8 bytes of the word containing one and the next eight containing the other.

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patent: 5936670 (1999-08-01), Frencken

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