Tiled memory addressing with programmable tile dimensions

Details Tiled memory addressing with programmable tile dimensions Tiled memory addressing with programmable tile dimensions

1995-12-21

1998-09-29

Kim, Matthew M.

Computer graphics processing and selective visual display system

Computer graphic processing system

Integrated circuit

345515, 711221, G06F 1206, G09G 536

Patent

active

058151680

ABSTRACT:
A display controller for a computer or the like stored display data in a tiled format in a display memory. Tile shape may be dynamically altered depending upon display mode (resolution, pixel depth, or the like) or other display factors. Tile shape (height versus width) may be optimized for different types of display (e.g., video, text, graphics, or the like). A display memory address conversion apparatus may receive pixel position data (e.g., from a BIT BLT engine or the like) and tile shape data and convert pixel position data to a tiled display memory address.

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