Tiled linear host texture storage

Details Tiled linear host texture storage Tiled linear host texture storage

1996-12-30

1998-12-01

Tung, Kee M.

Computer graphics processing and selective visual display system

Computer graphic processing system

Interface

345501, 345517, 345523, 345430, 345507, G06F 1300

Patent

active

058445765

ABSTRACT:
A process and implementing computer system for graphics applications in which polygon information, including transparency, color and other polygon characteristics, is organized, stored and transferred in terms of areas or tiled blocks of information in a matrix configuration. The polygon bytes of texel information are organized in an exemplary 8.times.8 matrix row and column format in the graphics subsystem for improved cache-hit efficiency and translated to and from the linear addressing scheme of a host storage device when the host storage is accessed to refill the graphics cache. The bytes comprising the memory tiles of polygon information are arranged such that a complete tile of information is transferred in one burst-mode host memory access to minimize normal multi-line access arbitration and other typical access delays.

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