Tile memory mapping for increased throughput in a dual bank acce

Details Tile memory mapping for increased throughput in a dual bank acce Tile memory mapping for increased throughput in a dual bank acce

1996-08-08

1998-07-14

Kim, Matthew M.

Computer graphics processing and selective visual display system

Computer graphic processing system

Integrated circuit

345515, 711105, 711202, G06F 1206

Patent

active

057812004

ABSTRACT:
A method and apparatus for configuring memory within a dual access dynamic random access memory (DRAM) frame buffer so that array conflicts are reduced between neighboring pixels. The present invention DRAM frame buffer contains a number of arrays (e.g., 48), each array containing a number of rows (e.g., 256), each row contains a number of bytes (e.g., 1024). Rows of arrays are used to store frame buffer information within the DRAM. There is a single row of sense amplifiers per array, so rows of the same array conflict since they cannot be open at the same time. In an alternative embodiment, some neighboring arrays share the same row of sense amplifiers so neighboring arrays can conflict. The DRAM memory is configured such that for any given central pixel, its four spatially neighboring pixels (up, down, right and left) are not stored (1) in a different row of the same array as the central pixel nor (2) stored in a different row of any other conflicting array. Under this memory configuration, a row storing a neighboring pixel can be pre-opened with an activate memory access in the same cycle as a memory read/write access involving the central pixel, thus increasing memory access throughput. Particular memory configurations are given for screen displays of 640.times.480 (8/16/24 bpp), 800.times.600 (8/16/24 bpp), 1024.times.768 (8/16 bpp), and 1280.times.1024(8 bpp).

REFERENCES:
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patent: 5473566 (1995-12-01), Rao
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patent: 5528751 (1996-06-01), Priem et al.
patent: 5581513 (1996-12-01), Rao

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