Tightly coupled multiple instruction multiple data computer syst

Details Tightly coupled multiple instruction multiple data computer syst Tightly coupled multiple instruction multiple data computer syst

1981-03-23

1983-10-25

Heckler, Thomas M.

Boots, shoes, and leggings

G06F 702, G06F 1516

Patent

active

044122861

ABSTRACT:
A concurrent processing system utilizes a generalized linearly expandable data transfer bus architecture to tightly couple data processors, memory and I/O devices. The system is suitable for multiple instruction multiple data processing, and operates by transmitting and receiving complete transaction codes fully identifying the target device by specifying a process code. Data processing memories and I/O devices may be dynamically assigned to a process by specifying the process code thus providing great flexibility in utilization of system resources. Processors, memories and I/O devices are connected together by means of interfaces which are connected to a bidirectional bus. The complete data transaction preferably occurs during one clock period, although four additional clock periods are used to complete a bus transaction, namely, arbitration, match recognition, data validation and acknowledgement of receipt.
All the interfaces examine each transaction on the bus 5 preferably simultaneously, and allow the transaction to pass to a device and or I/O, if control registers in the interfaces correspond to those of transaction.
The five bus transactions are overlapped in time so that a data transfer may occur with each clock cycle resulting in a data pipeline system of very high data transfer rates.

REFERENCES:
patent: 3768074 (1973-10-01), Sharp et al.
patent: 4214305 (1980-07-01), Tokita et al.
patent: 4223380 (1980-09-01), Antonaccio et al.
"Analysis of Multiple-Microprocessor System Architectures", Computer Design, Alan J. Weissberger, Jun. 1977.
"Multi-processors: An Overview and Working Example", Evolution of Computer Building Blocks, Samuel H. Fuller et al., pp. 463-484.

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