Tightly controlled output level CMOS-PECL driver

Details Tightly controlled output level CMOS-PECL driver Tightly controlled output level CMOS-PECL driver

1999-05-13

2001-05-15

Nelms, David (Department: 2818)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C326S071000

Reexamination Certificate

active

06232803

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates to Complementary Metal Oxide Semiconductor-Positive Emitter Coupled Logic (CMOS-PECL) drivers.
BACKGROUND OF THE INVENTION
Today's computer networks handle an ever-increasing amount of data. Fast Ethernet transmits and receives packets at rates of at least 100 Mbps., and other technologies such as asynchronous transfer mode (ATM) also require high data rates.
Very high speed applications traditionally use current-switching technologies known as emitter-coupled logic (ECL) gates and drivers.
CMOS typically operates with a power supply of 5V or 3.3V, but ECL traditionally operates with a negative power supply. Thus, standard ECL levels are not generally compatible with CMOS. A positive-voltage-shifted ECL, known as pseudo-ECL (PECL), has been used for CMOS chips using ECL-type current drivers.
ECL current drivers are often used to drive differential signals. Using a pair of signals rather than just one signal reduces sensitivity to noise and interference, since interference usually affects both signals equally, while not affecting the voltage difference between the two signals, nor the difference in current driven to each signal.
FIGS. 1 and 2
show conventional application circuits of a CMOS-PECL driver. Specifically,
FIG. 1
is a schematic representation of a PECL output circuit
1
connecting with a 50&OHgr;termination resistor
2
.
The output DC levels of the circuit of
FIG. 1
, V
OL
and V
OH
, are functions of source voltage, V
DD
, electron mobility, &mgr;
p
, threshold voltage, V
T
and temperature. Estimations from quick calculations show that the variations of both V
OL
and V
OH
are roughly equivalent to about ±600 mV. Variations on V
DD
account for about 60% of the output voltage variation and the other 40% is contributed from variations of manufacturing process specifications and temperature.
Therefore, there is a need to develop a new CMOS-PECL driver that delivers a tightly controlled output level under different operating conditions and over wide-tolerance manufacturing process specifications.
FIG. 3
is a detailed circuit diagram of the CMOS-PECL driver circuit
1
. Referring to
FIG. 3
, the output of a phase splitter circuit
4
is connected to a plurality of NAND gates
20
, a plurality of inverters
21
a-c,
and a plurality of FETs
22
a,b.
For ease of illustration, only one NAND gate
20
, and one of each set of inverters
21
a-c
is shown. However, as illustrated in
FIG. 3
, the notation 10X denotes a set of 10 components of each selected minimum unit value type, and the notation 2X denotes a set of
2
components of the selected minimum value type. That is, the 2X and 10X notations in
FIG. 3
are placed there to indicate the relative size of each device that can be referenced to a minimum unit device.
Therefore, in the conventional output structure, a two-input NAND gate
20
receives as its inputs, input signals A and EN. NAND gate
20
is connected in series with a first inverter
21
a
which is connected in series with a second inverter
21
b
to form a buffer. The output of the second inverter
21
b
is provided to the gate terminal of FET
22
a.
The source terminal of FET
22
a
is connected with voltage source V
DD
.
Inverter
21
c
receives as its input, signal EN. The output of the inverter
21
c
is provided to the gate terminal of FET
22
b.
The source terminal of FET
22
b
is connected with voltage source V
DD
. The drain terminals of FETs
22
a,b
are connected together, which provide output signal Z.
However, these conventional CMOS-PECL drivers fail to deliver a tightly controlled output level under different operating conditions and over wide-tolerance manufacturing process specifications.
Most of the known conventional circuits which attempt a solution to this problem are of the analog, feedback type. These circuits monitor and/or sense either PECL driver outputs or a dummy replica input/output (I/O) structure and then compare them with either internal and/or external preset reference voltages V
OL
and V
OH
, and generate bias voltages for the actual I/O structures.
SUMMARY OF THE INVENTION
The present invention solves the problem of providing a CMOS-PECL driver that delivers a tightly controlled output level under different operating conditions and over wide-tolerance manufacturing specifications by a digital, feed-forward circuit.
The circuit is comprised of a V
DD
potential detection circuit and a combined process and temperature detection circuit. Additionally, the circuit comprises an encoder circuit and an enabler and decoder circuits as well as a segmented output circuit.
The output circuit is segmented into identical modules while implementing a power scheme that is used to shut down inactive comparators that are employed in low power DC application flash ADCs.
Briefly, the circuit generates V
DD
and process-plus-temperature dependent signals and digitally encodes the control signals from 2
n
to N lines to reduce wiring complexity. These encoded lines may be shared with other on-chip PECL drivers. An enabling technique updates control signals only during the TX OFF (transmission off) state to avoid causing jitters and/or corruptions with transmitting signals. The N lines are then locally decoded back to the 2
n
lines for controlling PECL output structure modules.


REFERENCES:
patent: 5506803 (1996-04-01), Jex
patent: 5525914 (1996-06-01), Cao et al.
patent: 5576656 (1996-11-01), McClure
patent: 5581209 (1996-12-01), McClure
patent: 5874209 (1999-02-01), Manobar et al.
See Figures 1-3 of the application.

Affiliated with

Also associated with

Rating

Tightly controlled output level CMOS-PECL driver does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Tightly controlled output level CMOS-PECL driver, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Tightly controlled output level CMOS-PECL driver will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2494081