Thyristor with enhancement and depletion mode FET control for im

Details Thyristor with enhancement and depletion mode FET control for im Thyristor with enhancement and depletion mode FET control for im

1982-04-08

1984-08-14

Clawson, Jr., Joseph E.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 23D, 357 42, 357 86, 307252A, 307252C, H01L 2978

Patent

active

044660103

ABSTRACT:
A thyristor with gate-controlled emitter short-circuits designed as MIS structures of which a first part is switched off only for the duration of the ignition operation to form stabilization short-circuits, and a second, larger part is switched on only during quenching operation to form quenching short-circuits. The number of quenching short-circuits is established so that the emitter short-circuits effective during the quenching take up between 10% up to 80% of that part of the cross-sectional surface of the thyristor taken up by the totality of the emitter regions.

REFERENCES:
patent: 3891866 (1975-06-01), Okuhara et al.
patent: 4224634 (1980-09-01), Suedberg

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