Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with other solid-state active device in integrated...
Reexamination Certificate
2005-05-04
2009-08-11
Jackson, Jr., Jerome (Department: 2894)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Combined with other solid-state active device in integrated...
C438S133000, C363S027000, C365S094000, C365S104000, C365S105000
Reexamination Certificate
active
07573077
ABSTRACT:
In accordance with an embodiment of the present invention, a thyristor-based semiconductor memory device may comprise an array of thyristor-based memory formed in an SOI wafer. A supporting substrate may be formed with a density of dopants sufficient to assist delivery of a bias level to the backside of an insulating layer beneath a thyristor. Such conductivity within the substrate may allow reliable back-gate control for the gain of a component bipolar device of the thyristor.
REFERENCES:
patent: 4759030 (1988-07-01), Murayama et al.
patent: 4965872 (1990-10-01), Vasudev
patent: 5448104 (1995-09-01), Yallup
patent: 5627401 (1997-05-01), Yallup
patent: 6229161 (2001-05-01), Nemati et al.
patent: 6448586 (2002-09-01), Nemati et al.
patent: 6462359 (2002-10-01), Nemati et al.
patent: 6492662 (2002-12-01), Hsu et al.
patent: 6512274 (2003-01-01), King et al.
patent: 6528356 (2003-03-01), Nemati et al.
patent: 6545297 (2003-04-01), Noble, Jr. et al.
patent: 6552398 (2003-04-01), Hsu et al.
patent: 6583452 (2003-06-01), Cho et al.
patent: 6611452 (2003-08-01), Han
patent: 6627924 (2003-09-01), Hsu et al.
patent: 6790713 (2004-09-01), Horch
patent: 2001/0017392 (2001-08-01), Comfort et al.
patent: 2004/0156233 (2004-08-01), Bhattacharyya
Farid Nemati et al., U.S. Appl. No. 10/706,162, filed Nov. 12, 2003,Thyristor Circuit and Approach for TemperatureStability, assigned to the assignee of the present application.
F.Nemati and J.D. Plummber,A Novel High Density, Low Voltage SRAM Cell with a Vertical NDR Device, VLSI Technology Technical Digest, 1998.
F.Nemati and J.D. Plummber,A Novel Thyristor-based SRAM Cell(T-RAM)for High-Speed, Low-Voltage, Giga-Scale Memories, International Electron Device Meeting Technical Digest 1999.
National Scientific Corp.,TMOS Memory Cell, Breakthrough Technology in SRAM, at http://www.nsclocators.com/images/pdf/IP—tmos-2003.PDF, 2003.
R.Colin Johnson,Hybrid Tunnel Diodes Could Leapfrog Moore's Law, EE Times, Oct. 29, 2003, also at www.eetimes.com/at
ews/OEG20031029S0015.
Fields IP, PS
Jackson, Jr. Jerome
T-RAM Semiconductor, Inc.
Valentine Jami M
LandOfFree
Thyristor-based semiconductor memory device with back-gate bias does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Thyristor-based semiconductor memory device with back-gate bias, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Thyristor-based semiconductor memory device with back-gate bias will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4067357