Thyristor-based device having dual control ports

Semiconductor device manufacturing: process – Including control responsive to sensed condition

Reexamination Certificate

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C438S138000, C257SE21529

Reexamination Certificate

active

07320895

ABSTRACT:
Switching operations, such as those used in memory devices, are enhanced using a thyristor-based semiconductor device adapted to switch between a blocking state and a conducting state. According to an example embodiment of the present invention, a thyristor-based semiconductor device includes a thyristor having first and second base regions coupled between first and second emitter regions, respectively. A first control port capacitively couples a first signal to the first base region, and a second control port capacitively couples a second signal to the second base region. Each of the first and second signals have a charge that is opposite in polarity, and the opposite polarity signals effect the switching of the thyristor at a lower power, relative to the power that would be required to switch the thyristor having only one control port. In this manner, power consumption for a switching operation can be reduced, which is useful, for example, to correspond with reduced power supplied to other devices in a semiconductor device employing the thyristor.

REFERENCES:
patent: 3664942 (1972-05-01), Havas et al.
patent: 3943549 (1976-03-01), Jaecklin et al.
patent: 4031412 (1977-06-01), Ohhinata et al.
patent: 4032955 (1977-06-01), Anthony et al.
patent: 4612448 (1986-09-01), Strack
patent: 4672410 (1987-06-01), Miura et al.
patent: 4673962 (1987-06-01), Chatterjee et al.
patent: 4677455 (1987-06-01), Okajima
patent: 4734384 (1988-03-01), Tsuchiya
patent: 4829357 (1989-05-01), Kasahara
patent: 4833516 (1989-05-01), Hwang et al.
patent: 4864168 (1989-09-01), Kasahara et al.
patent: 4959703 (1990-09-01), Ogura et al.
patent: 4982258 (1991-01-01), Baliga
patent: 5034785 (1991-07-01), Blanchard
patent: 5099300 (1992-03-01), Baliga
patent: 5106776 (1992-04-01), Shen et al.
patent: 5202750 (1993-04-01), Gough
patent: 5252845 (1993-10-01), Kim et al.
patent: 5283456 (1994-02-01), Hsieh et al.
patent: 5321285 (1994-06-01), Lee et al.
patent: 5324966 (1994-06-01), Muraoka et al.
patent: 5390145 (1995-02-01), Nakasha et al.
patent: 5396454 (1995-03-01), Mowak
patent: 5412598 (1995-05-01), Shulman
patent: 5463344 (1995-10-01), Temple
patent: 5464994 (1995-11-01), Shinohe et al.
patent: 5528062 (1996-06-01), Hsieh et al.
patent: 5543652 (1996-08-01), Ikeda et al.
patent: 5641694 (1997-06-01), Kenney
patent: 5689458 (1997-11-01), Kuriyama
patent: 5705835 (1998-01-01), Nishiura et al.
patent: 5821549 (1998-10-01), Talbot et al.
patent: 5874751 (1999-02-01), Iwamuro et al.
patent: 5910738 (1999-06-01), Shinohe et al.
patent: 5914503 (1999-06-01), Iwamuro et al.
patent: 5936267 (1999-08-01), Iwamuro
patent: 5939736 (1999-08-01), Takahashi
patent: 5981984 (1999-11-01), Iwaana et al.
patent: 6081002 (2000-06-01), Amerasekera et al.
patent: 6210981 (2001-04-01), Birdsley et al.
patent: 6225165 (2001-05-01), Noble, Jr. et al.
patent: 6229161 (2001-05-01), Nemati et al.
patent: 6258634 (2001-07-01), Wang et al.
patent: 6281025 (2001-08-01), Ring et al.
patent: 6391689 (2002-05-01), Chen
patent: 6448586 (2002-09-01), Nemati et al.
patent: 6462359 (2002-10-01), Nemati et al.
patent: 6472693 (2002-10-01), Takahashi et al.
patent: 2001/0024841 (2001-09-01), Noble, Jr. et al.
patent: 2002/0093030 (2002-07-01), Hsu et al.
patent: 2002/0096690 (2002-07-01), Nemati et al.
patent: 2002/0100918 (2002-08-01), Hsu et al.
patent: 2110326 (1972-06-01), None
patent: 57208177 (1982-12-01), None
patent: 05235332 (1993-09-01), None
patent: WO-99/63598 (1999-12-01), None
patent: WO-2073695 (2002-09-01), None
Christopher J. Petti and James D. Plummer, The Field-Assisted Turn-Off Thyristor: A Regenerative Device with Voltage-Controlled Turn-Off, Aug. 1992.
Plummer, James, D. and Scharf, Brad, W., Insulated-Gate Planar Thyristors: I-STructure and Basic Operation, pp. 380-386, Feb. 1980.
S. M. Sze, Physics of Semiconductor Devices, Second Edition, John Wiley & Son, pp. 198-209, 1981.
Ponomarev, Y.V., Stolik, P.A. Salm, C., Schmitz, J., and Woerlee, P.H., High-Performance Deep SubMicron CMOS Technologies with Polycrystalline-SeGe Gates, IEEE Transactions on Electronic Devices, vol. 47, No. 4, p. 848-855.
Ponomarev et al., A 0.13 um Poly-SiGe Gate CMOS Technology for Low-Voltage Mixed-Signal Applications, IEEE Transactions on Electronic Devices, vol. 47, No. 7, pp. 1507-1513, Jul. 2000.
Ponomarev, Y.V., Schmitz, J., Woerlee, P.H., Stolk, P.A., and Gravesteijn, D.J., Gate-Workfunction Engineering Using Poly-(Se, Ge) for High Performance 0.18 um CMOS Technology, IEDM Tech. Dig., pp. 829-832, 1997.
Gribnikov, Z.S., Korobov, V.A., and Mitin, V.V., The Tunnel Diode As A Thyristor Emitter, Solid-State Electronics, vol. 42, No. 9, pp. 1761-1763.
Baliga, B. Jayant, Modern Power Devices, pp. 349-350, 1987.
Digh Hisamoto, Wen-Chin Lee, Jakub Kedzierski, Hideki Takeuchi, Kazuya Asano, Charles Kuo, Erik Anerson, Tsu-Jae King, Jeffrey Bokor and Chenming Hu, FinFET-A Self-Aligned Double-Gate MOSFET Scalable to 20 nm, Dec. 2000.
Xuejue Huang, Wen-Chin Lee,Charles Kuo, Digh Hisamoto, Leland Chang, Jakub Kedzierski, Erik Anderson, Hideki Takeuchi, Yang-Kyu Choi, Kazuya Asano, Vivek Subramanian, Tsu-Jae King, Jeffrey Bokor and Chenming Hu, Sub 50-nm FinFET; PMOS, Sep. 1999.
K. DeMeyer, S. Kubicek and H. van Meer, Raised Source/Drains with Disposable Spacers for sub 100 nm CMOS Technologies, Extended Abstracts of International Workshop on Junction Technology 2001.
Mark Rodder and D. Yeakley, Raised Source/Drain MOSFET with Dual Sidewall Spacers, IEEE Electron Device Letters, vol. 12, No. 3, Mar. 1991.
Yang-Kyu Choi, Daewon Ha, Tsu-Jae King and Chenming Hu, Nanoscale Ultrathin PMOSFETs with Raised Selective Germanium Source/Drain, IEEE Electron Device Letters, vol. 22, No. 9, Sep. 2001.
N. Lindert, Y. K. Choi, L. Chang, E. Anderson, W. C. Lee, T. J. King. J. Bokor, amd C. Hu, Quasi-Planar FinFETs with Selectively Grown Germanium Raised Source/Drain, 2001 IEEE International SOI Conference, Oct. 2001.
T. Ohguro, H. Naruse, H. Sugaya, S. Nakamura, E. Morifuji, H. Kimijima, T. Yoshitomi, T. Morimoto, H.S. Momose, Y. Katsumata, and H. Iwai, High Performance RF Characteristics of Raised Gate/Source/Drain CMOS with Co Salicide, 1998 Symposium on VLSI Technology Digest of Technical Papers, 1998.
Hsiang-Jen Huang, Kun-Ming Chen, Tiao-Yuan Huang, Tien-Sheng Chao, Guo-Wei Huang, Chao-Hsin Chien, and Chun-Yen Chang, Improved Low Temperature Characteristics of P-Channel MOSFETs with Si1-xGex Raised Source and Drain, IEEE Transactions on Electron Devices, vol. 48, No. 8, Aug. 2001.
Nemati, Farid, and Plummer, James, D., “A Novel High Density, Low voltage SRAM Cell with a Vertical NDR Device,” VLSI Technology Technical Digest, Jun. 1998.
Stanley Wolf Ph.D. and Richard N. Tauber Ph.D., Silicon Processing for the VLSI Era, vol. 1, 1986, p. 285-286.
Nemati, Farid, and Plummer, James, D., “A Novel Thyristor-Based SRAM Cell (T-RAM) for High Speed, Low Voltage, Giga-Scale Memories,” International Electron Device Meeting Technical Digest, 1999.
Digh Hisamoto, Toru Kaga and Eiji Takeda, Impact of the Vertical SOI “DELTA” Structure on Planar Device Technology. Jun. 1991.

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