Through-via and method of forming

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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C438S218000, C438S221000, C438S231000, C438S243000, C438S308000, C257SE21548

Reexamination Certificate

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07985655

ABSTRACT:
In one embodiment, a method of forming a via includes providing a semiconductor substrate, wherein the semiconductor substrate comprises a through-via region, forming isolation openings and a sacrificial feature in the through-via region, filling the isolation openings to form isolation regions, forming a dielectric layer over the semiconductor substrate after filling the isolation openings, forming a first portion of a through-via opening in the dielectric layer, forming a second portion of the through-via opening in the semiconductor substrate, wherein forming the second portion of the through-via opening comprises removing the sacrificial feature, and forming a conductive material in the first portion and the second portion of the through-via opening.

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Office Action mailed Apr. 14, 2010 on U.S. Appl. No. 12/277,458.
Lee, K. W. et al.; “Three-Dimensional Shared Memory Fabricated Using Wafer Stacking Technology”; Electron Devices Meeting, 2000 IEDM Technical Digest; Dec. 10-13, 2000; pp. 165-168.
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Office Action mailed in U.S. Appl. No. 12/277,458.

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