Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1997-01-23
1999-11-30
Bowers, Charles
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438296, 438424, 438430, 257354, 257374, 257386, H01L 2176
Patent
active
059942029
ABSTRACT:
A semiconductor MOSFET device is formed on a silicon substrate which includes trenches filled with Shallow Trench Isolation dielectric trench fill structures and extending above the surface of the substrate. The trench fill structures have protruding sidewalls with channel regions in the substrate having corner regions adjacent to the trench fill structures. The channel regions are between and adjacent to the STI trench fill structures doped with one concentration of dopant in the centers of the channel regions with a higher concentration of dopant in the corner regions. The dopant concentration differential provides a substantially equal concentration of electrons in the centers and at the corner regions of the channel regions.
REFERENCES:
patent: 4577395 (1986-03-01), Shibita
patent: 4589193 (1986-05-01), Goth et al.
patent: 4654120 (1987-03-01), Dougherty
patent: 4722910 (1988-02-01), Yasaitis
patent: 5021355 (1991-06-01), Dhong et al.
patent: 5059550 (1991-10-01), Tateoka et al.
patent: 5212106 (1993-05-01), Erb et al.
patent: 5215937 (1993-06-01), Erb et al.
patent: 5229316 (1993-07-01), Lee et al.
patent: 5258332 (1993-11-01), Horioka et al.
patent: 5275965 (1994-01-01), Manning
patent: 5281550 (1994-01-01), Ducreau
patent: 5292683 (1994-03-01), Dennison et al.
patent: 5298110 (1994-03-01), Schoenborn et al.
patent: 5300447 (1994-04-01), Anderson
patent: 5396096 (1995-03-01), Akamatsu et al.
patent: 5408116 (1995-04-01), Tanaka et al.
patent: 5482878 (1996-01-01), Burger et al.
patent: 5506168 (1996-04-01), Morita et al.
patent: 5607875 (1997-03-01), Nishizawa et al.
patent: 5677229 (1997-10-01), Morita et al.
patent: 5741738 (1998-04-01), Mandelman et al.
Bryant et al., "Characteristics of CMOS Device Isolation for the ULSI Age", IEDM Tech. Dig., pp. 671-674 (1994).
K. Shibahara et al., "Trench Isolation with DEL(NABLA)- shaped Buried Oxide for 256Mega-bit DRAMS" IEDM 92, pp. 275-278 (1992).
G. Fuse, et al., "A Practical Trench Isolation Technology with a Novel Planarization Process" IEDM 87, pp. 732-735 (1987).
P.C. Fazan and V. K. Matthews, "A Highly Manufacturable Trench Isolation Process for Deep Submicron DRAMS", IEDM 93, pp. 57-60 (1993).
D. S. Wen, "Optimized Shallow Trench Isolation Structure and Its Process for Eliminating Shallow Trench Isolation-Induced Parasitic Effects" IBM Tech. Dis. Bull., pp. 276-277 (Apr., 1992).
B.E.E. Kastenmeier et al "Chemical Dry Etching of Silicon Nitride and Silicon Dioxide Using CF4/02/M2 Gas Mixtures", J. Vac. Sci. Technol. A 14(5) pp. 2802-2803 (Sep./Oct. 1996).
Bryant et al, "The Current-Carrying Corner Inherent to Trench Isolation" IEEE Electron Device Letters, vol. 14, No. 8 412-414 (1993).
Bronner Gary Bela
Gambino Jeffrey Peter
Mandelman Jack Allan
Nesbit Larry Alan
Blum David S
Bowers Charles
International Business Machines - Corporation
Jones II Graham S.
Schnurmann H. Daniel
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