Threshold voltage setting circuit for reference memory cell...

Details Threshold voltage setting circuit for reference memory cell... Threshold voltage setting circuit for reference memory cell...

1999-12-28

2001-07-31

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185190, C365S185200

Reexamination Certificate

active

06269022

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a threshold voltage setting circuit for a reference memory cell for immediate and accurate setting of a threshold voltage without time consumption; and a method for setting a threshold voltage using the same.
2. Background of the Related Art
FIG. 1
illustrates a circuitry system of a related art threshold voltage setting circuit for a reference memory cell.
Referring to
FIG. 1
, the related art threshold voltage setting circuit for a reference memory cell is provided with a plurality of memories
2
each having a gate terminal connected to a wordline
3
, and a drain terminal connected to a bitline. There is an inverter connected to an initial input terminal of each wordline
3
. There is a selection transistor
5
connected between a cascode device
6
and a drain terminal of respective memories
2
for connection of a column load device
7
to a pertinent memory
2
through the cascode device
6
. There is an inverter between a gate terminal and a source terminal of the cascode device
6
for inverting a signal from a source terminal and providing to the gate terminal. There is a plurality of reference memory cell
9
each having a source, a drain, a control gate and a floating gate and connected to a reference column load device
12
through respective selection device
10
and cascode device
11
. There is an inverter between the gate terminal and the source terminal of the cascode device
11
for inverting a signal from the source terminal and providing to the gate terminal. And, there is a sense amplifier
8
having an SIN terminal with a voltage level of a contact node CN
1
of the column load device
7
and the cascode device
6
applied thereto and a RIN terminal with a voltage level of a contact node CN
2
of the column load device
12
and the cascode device
11
applied thereto. There is a switch SW between the contact node CN
1
and the SIN for controlling a path for transmitting a signal from the contact node CN
1
to the SIN terminal, and there is an NMOS transistor
16
for providing a signal to a pad
15
under the control of the controller
14
when the switch SW is closed. The sense amplifier
8
compares the signal to the SIN terminal to the signal to the RIN terminal. The floating gates of respective reference memory cells
9
are programmed to levels different from one another. In order to program the reference memory cells
9
to different levels, there is a voltage switch
13
for applying charge pulses to the reference memory cells
9
until respective memory cells
9
store target charge amounts. And, there is a controller
14
for controlling the voltage switch
13
the selection device
10
, the NMOS transistor and the switch SW. The foregoing related art circuit for setting a threshold voltage for a reference memory cell set the target threshold voltage accurately using a characteristic curve of a load connected to the bitline in the reference memory cell, and provides many program pulse combinations in programming the reference memory cell for minimizing a time period required for programming up to the target threshold voltages. Initially, a program pulse width is made large to permit a threshold voltage shift greater, and the program pulse width is made the smaller gradually as the threshold voltage approaches to a target value the more as the programing is repeated, for securing accuracy to the maximum and minimizing a time period required for reaching to the target threshold voltage. The controller
14
makes the program pulse combinations and sets up a reference for program verification. After programming the reference memory cell, a program verification is made, for verifying reach of the threshold voltage to the target value. And, if not reached to the target, the programming/program verification is repeated until the threshold voltage of the reference memory cell is reached to the target threshold voltage. In other words, in order to initialize more than one reference memory cells having different threshold voltages, accurate verifying reference voltages are applied externally through the controller
14
, and a plurality of program pulse combinations are used for reducing an overall program time period.
However, the related art circuit for setting a threshold voltage for a reference memory cell has the following problems.
First, the verification of an injected charge amount required whenever the program pulses are provided to the reference memory cells causes a time period required for reaching to the target threshold voltage longer.
Second, the controller required for using a method, in which, a program pulse width is made large initially and the program pulse width is made the smaller as the threshold voltage approaches to a target value causes the operation complicated.
Third, a resolution for making a final pulse width to approach to a desired target threshold voltage accurately is poor.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a threshold voltage setting circuit for a reference memory cell for immediate and accurate setting of a threshold voltage without time consumption, and a method for setting a threshold voltage using the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the threshold voltage setting circuit for a reference memory cell includes a reference memory cell having a source, a drain, a floating gate and a control gate, a first power source for applying a voltage to the drain of the reference memory cell under the control of the current detector when the reference memory cell is programmed, a second power source for supplying a voltage to the control gate of the reference memory cell when the reference memory cell is programmed or read, a third current connected to the source of the reference memory cell, a switch connected to the drain of the reference memory cell for controlling a path for external measuring of a current flowing to the reference memory cell in response to a measuring signal, and a current detector connected between the first power source and the drain of the reference memory cell for providing a stop signal to the first and second power sources to stop the programming of the reference memory cell forcibly when a current to the reference memory cell, which is monitored during the programming of the reference memory cell in response to a program signal, is the same with a reference stop current.
In other aspect of the present invention, there is provided the method for setting a threshold voltage by using a circuit for setting a threshold voltage for a reference memory cell, including the steps of (1) applying a voltage to the control gate for programming a selected unit reference memory cell in a reference memory cell unit, (2) closing a switch for measuring an initial current to the unit reference memory cell, (3) setting a first program stop reference current equal to, or slightly smaller than the initial current, (4) programming the selected unit reference memory cell by using the first program stop reference current according to an auto-verifying method, (5) fixing the voltage applied to the control gate of the selected unit reference memory cell and changing over to a read mode for measuring a current to the selected unit reference memory cell after the selected unit reference memory cell is programmed, (6) setting a target current

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