Threshold voltage convergence

Details Threshold voltage convergence Threshold voltage convergence

2001-12-05

2004-04-27

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185260, C365S185300, C365S185290

Reexamination Certificate

active

06728140

ABSTRACT:

BACKGROUND
1. Field of Invention
The invention is related to flash electronically erasable programmable read only memory (flash EEPROM), and more particularly to convergence of threshold voltages of flash EEPROM transistors.
2. Related Art
Flash EEPROM memory cells (typically field-effect transistors) are used as non-volatile memory that can be programmed in the field. Some flash EEPROM integrated circuits are designed to receive and output data using single terminals and are known as serial flash EEPROM. Other flash EEPROM integrated circuits are designed to receive and output data in parallel using multiple terminals and are known as parallel flash EEPROM.
In some instances all memory cells in an array of flash EEPROM memory cells are simultaneously erased in a single, bulk erase procedure. In other instances, only a sector of the memory cells in the array is erased. In still other instances, the data storage addresses for the memory cells in the array are partitioned into logical memory pages, and one or more unique pages are erased. Each page typically includes logical words (e.g., 8-bit bytes).
Flash EEPROM erase operations generally include two basic operations. The first (erase) procedure lowers the threshold voltage of all memory cells so that the cells each have an unprogrammed state. This erase procedure typically results in a distribution of threshold voltages among the cells being erased with some cells having their threshold voltages lowered below a specified minimum threshold voltage. These cells are considered over-erased. Thus a subsequent second (threshold voltage convergence) procedure raises unacceptably low threshold voltages. The threshold voltage convergence procedure further reduces the threshold voltage distribution for all memory cells being erased.
Software application designers, especially when working with serial flash EEPROM integrated circuits, require fast page erase operations to allow for subsequent reprogramming of the erased page. A disadvantage of present erase and convergence procedures, however, is that these procedures require too much time. In one instance, for example, 0.1 second (sec) erase and convergence pulses are used. What is required, therefore, is a method of speeding up flash EEPROM memory cell erase operations, especially the convergence procedure, and a flash EEPROM integrated circuit capable of carrying out this fast convergence procedure.
Flash EEPROMs typically include a small number of memory cells for which charge is more rapidly stored, removed, or lost than for the remaining cells. These “fast” cells may lose charge after being programmed such that their threshold voltage falls below the lower threshold voltage limit that signifies a cell is programmed. Other programmed memory cells may have a marginally low threshold voltage for various reasons. It is therefore also desirable to have a way to converge the threshold voltage distribution of programmed cells by raising marginally programmed cells without significantly affecting programmed cells that are well within the programmed threshold voltage range.
SUMMARY
A convergence signal includes a series of voltage pulses used to perform a convergence procedure in one or more flash EEPROM memory cells (transistors). In one instance subsequent voltage pulses in the convergence signal each have a higher voltage than the preceding pulse. The convergence signal having increasingly positive voltage pulses is applied to the control gate of a flash EEPROM transistor while the source, drain, and bulk regions of the transistor receive a negative voltage. The voltage pulses received by the control gate cause electrons to be drawn from the transistor's bulk channel region into the floating gate using Fowler-Nordheim tunneling. The pulse durations and voltages are selected to quickly raise the threshold voltage of transistors initially having low threshold voltages and to more slowly raise the threshold voltage of transistors initially having a higher threshold voltage. In another instance, subsequent voltage pulses in the convergence signal each have a longer duration than the preceding pulse.
An integrated circuit includes an array of memory cells and a control unit which controls the application of the convergence signal to one or more memory cells. The integrated circuit may be either serial flash EEPROM or parallel flash EEPROM in which bulk, sector, or page mode erasing is used.


REFERENCES:
patent: 5295107 (1994-03-01), Okazawa et al.
patent: 5357476 (1994-10-01), Kuo et al.
patent: 5412608 (1995-05-01), Oyama
patent: 5521867 (1996-05-01), Chen et al.
patent: 5602779 (1997-02-01), Gotou
patent: 5991203 (1999-11-01), Choi
patent: 6031766 (2000-02-01), Chen et al.
patent: 6094373 (2000-07-01), Saito
patent: 6118705 (2000-09-01), Gupta et al.
patent: 6249459 (2001-06-01), Chen et al.
patent: 2002/0167843 (2002-11-01), Hsia et al.
patent: 2003/0026132 (2003-02-01), Chen et al.
K. Oyama et al.,A Novel Erasing Technology for 3.3V Flash Memory with 64Mb Capacity and Beyond, IEDM Technical Digest (IEEE, 1992), at 607-610, 633 [6 pages total, including cover page].

Affiliated with

Also associated with

Rating

Threshold voltage convergence does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Threshold voltage convergence, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Threshold voltage convergence will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3275832