Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-05-09
2002-08-20
Elms, Richard (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185300
Reexamination Certificate
active
06438037
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of electronic data storage devices. More particularly, the present invention relates to non-volatile semiconductor memory devices having a compact threshold voltage distribution and a method for compacting the threshold voltage distribution for non-volatile semiconductor memory designs.
2. Description of the Related Art
Electronic data storage designs, referred to as memory, are used to store computer programs executed by an electronic processor and/or store logical data operated on by the processor to achieve the functionality of an electronic device. Semiconductor memory designs that do not require ambient power to store electronic data, commonly referred to as “non-volatile” semiconductor memory devices, have been developed. Flash memory is a specific form of non-volatile memory by which bits of logical data are stored in units of memory termed memory cells. A grouping of memory cells is termed a word, a grouping of words termed a page, and a grouping of pages termed a sector. Data is accessed for reading and programming by word or page, while an entire sector must be accessed for erasing. In general, the flash memory is arranged into columns and rows of memory cells, each column representing a bitline of a data.
A typical memory cell in a flash memory device includes a transistor characterized by a programmable threshold voltage V
t
. The transistor's threshold voltage can be set, or programmed, to a desired value along an analog scale between maximum and minimum threshold voltage limits that are determined based on the design parameters for the transistor. In one example, a flash memory cell has a discrete Metal-Oxide-Semiconductor (“MOS”) field effect transistor having a source, a drain, a floating gate, a control gate and a p-well substrate material. In conventional flash memory designs, known as NOR memory, the memory cells are arranged in an array of rows and columns, with the control gates of the transistors comprising a row being electrically coupled to a respective word-line and the drains comprising a column being electrically coupled to a respective bit-line. The sources of each memory cell are electrically coupled to each other.
Voltages can be applied to the transistor for setting the V
t
to represent logical value “1” or “0,” for reading the data stored in the memory cell, for verifying that the cell is programmed, for verifying that the cell is erased, and for verifying that the cell is not overerased. When a voltage sufficiently exceeding the V
t
is applied to the control gate, the transistor turns on and can be caused to conduct substantial current. Conversely, when a voltage applied to the gate does not sufficiently exceed the V
t
, the transistor will remain in an off state and will not conduct substantial current. In typical flash memory designs, the on state represents a logical “1” while the off state represents a logical “0.” For example, during a read cycle of a programmed memory cell, the voltage applied to the gate is not greater than V
t
and the memory cell will not conduct current. In comparison, an erased memory cell will conduct current during a read cycle because the gate voltage is greater than V
t
. Thus a programmed memory cell represents logical “0,” while and erased memory cell represents logical “1.”
In one example of a floating gate cell, the transistor is programmed by biasing the transistor in a manner to cause injection of electrons into the floating gate, and erased by biasing the transistor in a manner to cause electrons to evacuate the floating gate. In an example of a non-floating gate cell, a transistor with a thin insulating film between the substrate and control gate is programmed by biasing the transistor in a manner to cause injection of electrons to the thin insulating film, and erased by causing electrons to evacuate the thin insulating film. In general, electrons injected into the floating gate or the thin insulating film raises the V
t
, while evacuation of electrons decreases the V
t
.
By way of example, programming of the memory cell occurs by biasing the memory cell such that 9V is applied to the control gate, 5V is applied to the drain and the source is grounded (0V). This configuration causes electrons to be injected from the drain depletion region into the floating gate. After the memory cell is programmed the injected electrons are trapped, creating a negative charge that increases the V
t
of the memory cell. By way of example, a programmed memory cell has a V
t
greater than approximately 5V.
In one arrangement for reading data, the memory cell is biased by applying 5V to the word-line to which the control gate of the cell is connected, applying 1V to the bit-line to which the drain is connected, grounding the source, and sensing data on the bit-line. When data is read from a programmed memory cell, wherein V
t
is set relatively high (5V), the bit-line to which it is electrically coupled will not conduct substantial current. In comparison, when data is read from an erased memory cell, wherein V
t
is set relatively low, the control gate voltage creates a channel in which relatively high current will conduct on the bit line to which the erased memory cell is electrically coupled.
Erasure of data is caused by a process in which the transistor is biased in a manner to cause electrons to evacuate the floating gate or the thin insulating film, or by injection of holes into these regions. An erase voltage is applied at sufficient value and for a sufficient duration to lower the transistor's threshold voltage below that of a predetermined voltage, often referred to as the erase-verify voltage (“V
cv
”). The erase-verify voltage is sufficiently less than the voltage applied during the read cycles V
t
so that an erased transistor will conduct current during a read cycle. In one arrangement for erasing, a relatively high voltage, typically 12V, is applied to the source while the gate is grounded and the drain is floating. This arrangement causes electrons to undergo Fowler-Nordheim tunneling from the floating gate towards the source. In another arrangement, the memory cell is biased with a negative voltage substantially on the order of −10V applied to the control gate while +10V is applied to the source and the drain is floating. In a further arrangement, 5V is applied to a P-well and −10V is applied to the control gate while the source/drain are floating. Although present flash memory designs can be erased at the sector level and can be programmed at the word level, it will be appreciated that the granularity by which a flash memory device can be programmed or erased may vary and that granularities down to the bit level are contemplated.
During erasure of a flash memory, the threshold voltage of each memory cell is verified to have a value less than the erase verify voltage. Because of variations in the physical and electrical characteristics of the memory cells, the rate that a memory cell erases can vary. Design variables such as channel length and width affect how fast a transistor can be erased. Because each memory cell is subjected to substantially the same erase voltage pulse, some memory cells erase faster than others. Fast-erase memory cells can overerase, having a lower threshold voltage than a slow-erase memory cell. The erased memory cells collectively form a threshold voltage distribution with the fast-erase memory cells having a relatively low threshold voltage, slow-erase memory cells having a threshold voltage closer to the erase verify voltage and typical memory cells having a median erased threshold voltage. A typical distribution will be centered about the median threshold voltage.
An overerased memory cell exhibits behavior similar to a depletion mode type transistor that cannot be turned off by normal operating voltages applied to the control gate, and may introduce leakage currents during subsequent program and read operations. Furthermore, a transistor with an u
Fastow Richard
Guo Xin
Haddad Sameer S.
Advanced Micro Devices , Inc.
Elms Richard
Eschweiler & Associates LLC
Phung Anh
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