Threshold evaluation of EPROM cells

Details Threshold evaluation of EPROM cells Threshold evaluation of EPROM cells

2008-03-27

2009-10-13

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185200, C365S185090, C365S185020

Reexamination Certificate

active

07602646

ABSTRACT:
Evaluating an embedded EPROM in a host IC device involves using program circuitry to program/unprogram all of the floating-gate cells of the embedded EPROM, then simultaneously transmitting a predetermined test bias voltage to all of the programmed/unprogrammed floating-gate cells, and then evaluating the output terminals of all of the floating-gate cells using a logic (e.g., wired NOR or NAND) circuit, whereby successful operation of all of the embedded EPROM cells causes the wired logic circuit to generate a single positive test result signal, and the failure of one or more of the embedded EPROM cells causes the wired logic circuit to generate a single negative test signal. A reference cell is also evaluated using a bias testing circuit to determine that the reference voltage supplied during normal operation is at an acceptable voltage level.

REFERENCES:
patent: 6707718 (2004-03-01), Halim et al.
patent: 7200058 (2007-04-01), Mochizuki

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