Threshold dithering for time-to-digital converters

Details Threshold dithering for time-to-digital converters Threshold dithering for time-to-digital converters

2008-01-23

2011-11-08

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S156000, C327S157000

Reexamination Certificate

active

08054116

ABSTRACT:
Techniques for dithering quantization thresholds of time-to-digital converters (TDC's) in all-digital phase-locked loops (ADPLL's) are disclosed. In an embodiment, the delay introduced by an individual buffer in a TDC delay line may be dithered. In another embodiment, the delay associated with the TDC delay line may be extended by a fixed amount to accommodate dithering of the zero-delay threshold.

REFERENCES:
patent: 6429693 (2002-08-01), Staszewski et al.
patent: 2005/0184901 (2005-08-01), DaDalt
patent: 2005/0186920 (2005-08-01), Staszewski et al.
International Search Report and Written Opinion˜PCT/US2009-031595, International Searching Authority˜European Patent Office, Apr. 28, 2009.
Rahkonen T et al: “Time interval measurements using integrated tapped CMOS delay lines” 19890814; 198908140-019890816, Aug. 14, 1989, pp. 201-205, XP010090157.
Wenbo Liu et al: “A Test Strategy for Time-to-Digital Converters Using Dynamic Element Matching and Dithering” Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on Kobe Japan May 23-26, 2005, Piscataway, NJ, USA, IEEE, May 23, 2005, pp. 3809-3812, XP010816495, Section B. Time Internval Generation with Dithering, p. 3811, col. 1

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