Threshold-based load balancing in ATM switches with parallel swi

Multiplex communications – Wide area network – Packet switching

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370 61, 370 63, 370 67, H04L 1250, H04L 1254

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053553721

ABSTRACT:
An asynchronous transfer mode switching system uses a parallel array of switching planes, distributors for distributing cells between the switching planes, and resequencers for collecting the cells after they have been switched. To balance the loads in the output buffers of the switching planes, each distributor includes two one-cell buffers and a load matrix. The load matrix stores the state of the output buffers in the switching planes, and this information is used to decide whether to send a cell arriving at the first of the one-cell buffers to its scheduled switching plane or to store the cell in the other of the one-cell buffers until either a switching plane with a lightly loaded output buffer for the cell's destination becomes available or another later arriving cell needs to be stored there.

REFERENCES:
patent: 4545051 (1985-10-01), Belforte et al.
patent: 4701907 (1987-10-01), Collins
patent: 5191578 (1993-03-01), Lee
Suzuki et al. "Output Buffer Switch Architecture for Asynchronous Transfer Mode" IEEE Conference on Communications. Jun. 11-14, 1989 pp. 250-154.
Aramaki et al "Parallel ATOM Switch Architecture for High Speed ATM Networks", IEEE International Conference on Communications 1992, Chicago, Ill. pp. 311.1.1-311.1.5.

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