Three transistor high endurance EEPROM cell

Details Three transistor high endurance EEPROM cell Three transistor high endurance EEPROM cell

1988-04-08

1989-08-08

Hecker, Stuart N.

Static information storage and retrieval

Floating gate

Particular biasing

365187, 36518901, 357 235, 357 41, G11C 1134, G11C 700, H01L 2978, H01L 2702

Patent

active

048559555

ABSTRACT:
The memory cell of the present invention is a three transistor cell, including two floating gate MOS transistors connected in series with a select transistor. The source of the first memory cell floating gate memory transistor is connected to a source of a first potential. Its gate is connected to a first sense line. Its drain is connected to the source of the second memory cell floating gate transistor. The gate of the second memory cell floating gate transistor is connected to a second sense line. The drain of the second memory cell floating gate transistor is connected to the source of a select transistor. The gate of the select transistor is connected to a word line. The source of the select transistor is connected to a bit line.
A plurality of memory cells may be connected together as a byte, and may be placed in an array. The gates of the select transistors are connected together. A word line signal which drives the gates of the select transistors also drives the gates of two sense line byte select transistors which enable the sense line signals to appear on only the gates of the memory cell floating gate transistors of the selected byte.

REFERENCES:
patent: 4425631 (1984-01-01), Adam
patent: 4580247 (1986-04-01), Adam
patent: 4630085 (1986-12-01), Koyama
patent: 4636984 (1987-01-01), Neukomm
patent: 4677590 (1987-06-01), Arakawa
patent: 4752912 (1988-07-01), Guterman
Coffman, Tim, et al., A lMb CMOS EPROM with a 13.5.mu.m.sup.2 cell, Feb. 25, 1987, pp. 72-73, 1987 IEEE International Solid-State Circuits Conference.

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