Three transistor EEPROM cell

Static information storage and retrieval – Floating gate – Particular biasing

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365104, 36518908, 307465, 257315, G11C 700, G11C 1600

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active

051703734

ABSTRACT:
An EEPROM cell suitable for use in programmable logic devices contains three transistors. A floating gate transistor is used to retain a programmed value using charge storage on the floating gate. A read transistor is connected between the floating gate transistor and an output signal line, and used to access the value stored in the floating gate transistor. A write transistor is connected to the floating gate transistor opposite the read transistor, and is used when programming the floating gate transistor. The write transistor and its associated control circuitry are fabricated to handle the higher programming voltages required by the floating gate device. The read transistor and associated drive circuitry are not required to handle the higher programming voltages, and can be fabricated using smaller, faster devices.

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IEEE International Solid State Circuits Conference, `A 16ns CMOS EEPLA with Reprogrammable Architecture`; vol. 33, pp. 240-241, Feb. 1986, New York, U.S.
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IBM-TDB vol. 25, No. 1 Jun. 1985 by Chao Electrically Alterable Read Only Memory Array.

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