Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-08-27
2002-12-24
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S185290
Reexamination Certificate
active
06498752
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory and in particular to writing a one-transistor cell, NOR-type, nonvolatile memory array.
2. Discussion of Related Art
A typical one-transistor cell, NOR-type flash array is comprised of a plurality of cells disposed in multiple rows (word lines) and multiple columns (bit lines), and circuits that control a variety of memory operations. These memory operations include erase, program, correct, read, and verify. The drains of flash memory cells are connected together to the corresponding bit lines, which are selected by a y-decoder. The sources of the memory cells are typically connected to common source lines, and the gates are jointly tied to word lines which are selected by an X-decoder. For a CHE (channel hot electron) program operation in an ETOX, NOR-type flash array, +10V is transferred to the selected word line along with +5V and 0V applied to the selected bit line and source line, respectively. This causes, the Vt (threshold voltage) of selected cells to increase after the program operation is performed. In contrast to program operation, −10V and +5V are applied to the selected word lines and source lines, respectively, with the selected bit lines in a floating state during a block erase operation.
After cells have been erased, an erase verify is performed to detect any under erased cells that have threshold voltage, Vt, which is above a predetermined value, Vtmax. For example, Vtmax could be set to around +1.5V, and as long as one cell's Vt is above 1.5V, an erase pulse is further applied. A successful erase is defined when the Vt of all cells being erased is below +1.5V. Due to the variations of the characteristics of the cells, some cells will be erased faster with their Vt going below a minimum voltages, Vtmin, during erase operation. For example, Vtmin is typically set to be +0.5V, and some cells are erased to a negative threshold voltage, these cells are called “over-erased cells”. As a result, a leakage current will occur and false data will be read.
In U.S. Pat. No. 6,122,198 (Haddad et al.) a method is directed toward erase verify and over erase verify by using a bit-by-bit approach. The threshold voltage of each memory cell is compared to the Vt of a reference cell and an over erase correction pulse is applied to the column containing the over erased cell. The over erase correction is a type of program operation but using a lower voltage applied to the selected word line, which contains over erased cells, to bring the negative Vt of the over-erased cells back to acceptable positive range. As seen from
FIG. 1
of prior art, I
BL
is the total bit line current generated from the sum of I
1
, I
3
and I
4
when cell
504
is being erase verified, corrected, or programmed . The cells
502
,
506
and
508
conduct with I
1
, I
3
and I
4
leakage current, respectively, due to the negative Vt after erase. Cells of
502
,
506
and
508
are referred as over-erased cells. The current I
1
, I
3
and I
4
varies with bit line voltage, VD. During erase verify read, VD is approximately +1V, and current I
1
, I
3
and I
4
will be increased when the voltage VD is increased during the program or correction operation. The leakage current IBL may exceed the supply capability from an on-chip charge pump circuit. As a consequence, the over erased cells render the program and correction operations inoperative. Similarly, the over erase induced leakage current shown in
FIG. 2
of prior art can cause the erase verification not to perform correctly. If the sum of leakage current I
1
, I
3
and I
4
caused by the over erased cells is higher than the contact current of an ON cell, all the cells will be read as an ON cell, then the erase verification is always falsely passed.
FIG. 3
shows a flow diagram of prior art for detecting and correcting over erased cells. The column address is set to the first column within the array
100
and an address counter is set to zero
102
. A bad column flag is set to false
104
and the row address is set to the first cell in the column
106
. The addressed cell is measured to determine if the cell is over erased
108
. If the cell is over erased
108
, the over erased cell is programmed with a single pulse
110
and the bad column flag is set to true
112
, after which it is determined if the cell is the last cell in the column
114
. If the cell is not over erased
108
, it is determined if the cell is the last cell in the column
114
. If the cell is not the last cell in the column
114
, the row address is incremented
116
and the next cell in the column in measured for an over erase state
108
. If the cell is the last cell in the column
114
and if the bad column flag is true
118
, a counter is incremented
120
, and if the count exceeds a predetermined amount
122
, the repair fails and the process ends. If the count does not exceed a predetermined number
122
, the bad column flag is set to false
104
and the process is repeated. If the bad column is not true
118
and if the column is the last column
126
, the process is complete
125
. If the bad column is not true
118
and if the column is not the last column
126
, the column address is incremented
128
, the address counter is set to false
102
and the process is repeated on the next column. Because of the leakage current from other cells in a column as noted in
FIG. 2
, the cell
704
being measured for over erase cannot be accurately be verified; therefore, the procedure of
FIG. 3
will not work properly.
In
FIG. 4A
a flow diagram of prior art is shown for a bit-by-bit erase verify. The row address is set to the first row address
402
, and the column address is set to the first column address
404
. An erase verify is performed
406
on the addressed bit. If the addressed bit is under erased
408
, an erase pulse is applied to the memory array
409
and the addressed cell is erase verified
406
. If the addressed cell is not under erased
408
, and if it is not the last column
412
, the column address is incremented
410
, and the addressed bit in the next column is erase verified
406
. If it is not the last column
412
, the row address is incremented
414
, and the column address is set to the first address
404
. If it is the last row
416
, the row address is set to the first address
418
shown in FIG.
4
B.
In
FIG. 4B
is shown a flow diagram of prior art for a bit-by-bit over erase detection and correction. After the row address is set to the first address
418
, the column address is set to the first column address
420
, and the addressed cell is verified to be erased
422
. If the threshold voltage Vt of the addressed cell is not greater than a predetermined minimum
424
, an over erase correction pulse is applied to the addressed column
426
, and the address cell is again verified
422
. If the threshold voltage Vt of the addressed cell is greater than a predetermined minimum
424
, and if it is not the last column, the column address is incremented
428
. If it is the last column
430
, the row address is incremented
432
. If it is not the last column
430
, the addressed cell in the next column is verified for an erased Vt which is greater than a predetermined minimum
422
. If the last row has not been attained
434
, the column address is set to the first address
420
and the process continues. If the last row has been attained
434
, the row address is set to the first row
436
as shown in FIG.
4
C.
Shown in
FIG. 4C
is a flow diagram of prior art for a bit-by-bit under erase detection and correction. After the row address is set to the first address
436
, the column address is set to the first column address
438
. The addressed cell is erase verified
440
. If the addressed bit is under erased
442
, an erase pulse is applied to the array
443
, and the cell is again erase verified
440
.
If the addressed bit is not under erased
442
, the column address is incremented
444
, and if it is
Hsu Fu-Chang
Lee Peter W.
Tsao Hsing-Ya
Ackerman Stephen B.
Aplus Flash Technology Inc.
Hoang Huan
Saile George O.
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