Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
1996-01-11
2001-04-24
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
Reexamination Certificate
active
06222475
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an A/D converter for converting an analog signal into a digital signal.
2. Description of the Related Art
As the number of electronic devices which handle digital signal processing have greatly increased in recent times, there is a concomitant increase in the demand for A/D converters which convert analog signals into digital signals. A parallel comparison type (flash type) A/D converter, one type of A/D converter, needs 2
n
−1 comparators to acquire an n-bit digital output signal. As the number of bits in the digital output signal increases, the circuit scale increases exponentially. However a series-parallel comparison type (2-step parallel type) A/D converter needs fewer comparators, and thus can utilize a smaller circuit scale than the parallel comparison type A/D converter. Due to the recent increase in the number of bits in the digital output signal of A/D converters, there is a strong demand to make the circuit scale of the parallel comparison type A/D converter smaller.
The conventional 2-step parallel A/D converter is described in detail in IEEE-ISSCC, Report No. WAM-36, February 1982.
FIG. 1
is a circuit diagram showing the structure of the conventional 4-bit 2-step parallel A/D converter.
A high reference voltage V
RH
and a low reference voltage V
RL
are divided by the resistor string formed by 16 series-connected resistors R. Those resistors R have the same resistance. The resistor string is separated into four blocks B
1
to B
4
each consisting of four series-connected resistors R. The nodes between the blocks B
1
and B
2
, B
2
and B
3
, and B
3
and B
4
are connected to the inverting input terminals of associated comparators
10
to
12
. Reference voltages V
1
to V
3
respectively output from those three nodes are input to the inverting input terminals of the associated comparators
10
to
12
. The reference voltages V
1
to V
3
each have a value obtained by dividing the potential difference between the high reference voltage V
RH
and low reference voltage V
RL
by four.
Three nodes between the four resistors R, which constitute each of the blocks B
1
to B
4
, are connected via an associated set of three switches S
A
, S
B
, S
C
or S
D
to the inverting input terminals of comparators
20
to
22
. Reference voltages Va to Vc are respectively applied to the inverting input terminals of the comparators
20
to
22
.
An analog input signal A
in
is input to the non-inverting input terminals of the individual comparators
10
to
12
and
20
to
22
. The comparators
10
to
12
compare the associated reference voltages V
1
to V
3
with the analog input signal A
in
. Each comparator
10
,
11
or
12
outputs a signal of a low (L) level when the voltage level of the analog input signal A
in
becomes lower than that of the reference voltage V
1
, V
2
or V
3
, and outputs a signal of a high (H) level when the voltage level of the analog input signal A
in
becomes higher than that of the reference voltage V
1
, V
2
or V
3
. The output signals (thermometer codes) of the comparators
10
to
12
are input to a first encoder
40
. The first encoder
40
determines to which one of four large-level regions the voltage level of the analog input signal A
in
belongs: region V
RB
to V
1
, V
1
to V
2
, V
2
to V
3
and V
3
to V
RL
. Those four regions are acquired by dividing the potential difference between the high reference voltage V
RH
and low reference voltage V
RL
by four. The first encoder
40
encodes the result of the decision into a binary code and converts the binary code into a 2-bit digital output en
11
, en
10
.
Based on the digital output en
11
, en
10
, a switch control circuit (not shown) closes (enables) one set of switches S
A
, S
B
, S
C
or S
D
respectively corresponding to the first, second, third or fourth large-level region.
The reference voltages Va to Vc, obtained by further dividing the potential differences of the four large-level regions by four, are applied to the inverting input terminals of the associated comparators
20
to
22
via the closed switches S
A
to S
D
. The comparators
20
to
22
compare the associated reference voltages Va to Vc with the analog input signal A
in
. Each comparator
20
,
21
or
22
outputs an L-level signal when the voltage level of the analog input signal A
in
becomes lower than that of the reference voltage Va, Vb or Vc, and outputs an H-level signal when the voltage level of the analog input signal A
in
becomes higher than that of the reference voltage Va, Vb or Vc. The output signals of the comparators
20
to
22
are input to a second encoder
50
having the same structure as the first encoder
40
. The second encoder
50
determines to which one of four small-level regions the voltage level of the analog input signal A
in
belongs: reference voltage Va or above, between Va and Vb, between Vb and Vc, and Vc or below. These small-level regions are acquired by dividing the associated large-level regions by four. The second encoder
50
encodes the result of the decision into a binary code and converts the binary code into a 2-bit digital output en
21
, en
20
.
In the conventional 4-bit 2-step parallel A/D converter, as described above, the first A/D conversion is performed by the comparators
10
to
12
and the first encoder
40
, yielding the upper 2-bit digital output en
11
, en
10
. Then, based on the digital output en
11
, en
10
, the switches S
A
to S
D
are switched over, and the second A/D conversion is performed by the comparators
20
to
22
and the second encoder
50
, yielding the lower 2-bit digital output en
21
, en
20
.
FIG. 2
illustrates the circuit structure in the case where the aforementioned 4-bit 2-step parallel A/D converter is laid out on a semiconductor substrate. The resistors R and the switches S
A
to S
D
are laid out to form a rectangular pattern as a whole. The comparators
10
to
12
are arranged on the right side of the rectangle, with the first encoder
40
arranged outside the locations of the comparators. Arranged below the bottom side of the rectangle are the comparators
20
to
22
which perform the second A/D conversion. Arranged further outside the comparators
20
to
22
is the second encoder
50
which also performs the second A/D conversion. The layout on the substrate is given regularity by regularly arranging the comparators
10
to
12
and
20
to
22
and the encoders
40
and
50
around the regularly laid-out resistors R and switches S
A
to S
D
.
If the comparator
11
shown in
FIG. 2
is arranged to the left side of or above the rectangle formed by the resistors R and switches S
A
to S
D
, wiring connecting the inverting input terminal of the comparator
11
and the node between the blocks B
2
and B
3
does not pass over the individual resistors R and switches S
A
to S
D
, further facilitating the layout on the substrate. It should be noted that the order with which the voltages are applied to the inverting input terminals of the comparators
20
to
22
via the respective switches S
A
to S
D
in
FIG. 2
differs from the order of the application of the voltages to the inverting input terminals of the comparators
20
to
22
via the respective switches S
A
to S
D
in FIG.
1
. This is because the order with which the voltages are supplied to the comparators
20
to
22
in the first row (block B
1
) and the third row (block B
3
) of the resistor string is reverse to that in the second row (block B
2
) and the fourth row (block B
4
). Therefore, the second encoder
50
should be designed to reverse the order of the comparison results, which are output from the individual comparators
20
to
22
depending on which of the switches S
A
to S
D
is closed.
The 2-step parallel A/D converter shown in
FIGS. 1 and 2
needs a sample and hold circuit, not shown, which samples and latches the analog input signal A
in
so that the level of the analog input signal A
in
will not vary during the two A/D conversions.
If the number of bits is i
Fujitsu Limited
Staas & Halsey , LLP
Williams Howard L.
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