Three-state logic circuit for wire-ORing to a data bus

Details Three-state logic circuit for wire-ORing to a data bus Three-state logic circuit for wire-ORing to a data bus

1986-07-03

1987-07-21

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307455, 307475, 307557, H03K 1716

Patent

active

046820582

ABSTRACT:
A three-state logic circuit comprising a logic gate on a semiconductor chip which includes first and second conductors, respective resistors connected to the conductors, terminals for receiving input signals, and transistors for generating complementary output signals on the first and second conductors by passing respective currents through the resistors as a logical function of the input signals with the output signals having high and low voltage levels V.sub.H and V.sub.L ; a control circuit on the chip having a first terminal connected to the first conductor, a second terminal connected to the second conductor, and a control terminal for receiving a control signal; a switching circuit within the control circuit which responds to the control signal by passing identical control currents through the respective resistors and into the first and second terminals to thereby lower the voltage levels on both the first and second conductors by at least V.sub.H -V.sub.L ; and first and second driver transistors on the chip and respectively connected to the first and second conductors which drive complementary large and small currents off the chip in response to the voltage levels V.sub.H and V.sub.L, and which drive no more than the small current off the chip in response to the lowered voltage levels.

REFERENCES:
patent: 4382197 (1983-05-01), Kiyozuka
patent: 4410816 (1983-10-01), Kanai
patent: 4490630 (1984-12-01), Freeman
patent: 4596940 (1986-06-01), Schuppan et al.
patent: 4636990 (1987-01-01), Buscaglia et al.

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