Three state input circuits

Details Three state input circuits Three state input circuits

1982-01-07

1984-08-14

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307289, 307481, 307585, H03K 19096, H03K 1920, H03K 17693

Patent

active

044659440

ABSTRACT:
The three state input circuit includes a P channel MOS FET and an N channel MOS FET which are supplied with an input signal at their drain electrodes, and a pair of flip-flop circuits connected to source electrodes of respective FETS and acting as a memory. Gate electrodes of the FETs are supplied with timing signals. The circuit operates to sequentially and periodically judge the input states in accordance with the timing signals, and then the stores results of such judgements and then outputs the stored results as 2 bit binary signals.

REFERENCES:
patent: 4100429 (1978-07-01), Adachi
patent: 4163907 (1979-08-01), Schroeder et al.

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