Three-state CMOS output buffer circuit

Details Three-state CMOS output buffer circuit Three-state CMOS output buffer circuit

1996-03-26

1998-12-22

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

326 56, 327112, H03K 301

Patent

active

058523820

ABSTRACT:
A three-state CMOS output buffer circuit includes a final amplifier stage having a pull-up transistor and a pull-down transistor connected between a voltage supply and ground and having a common output node, and a control circuitry for driving the final amplifier stage including a first logic gate supplied with an input data signal and an enable/disable signal for activating a three-state mode in which the pull-up transistor and the pull-down transistor are both deactivated, the first logic gate driving the pull-up transistor, a second logic gate supplied with said input data signal and enable/disable signal, the second logic gate driving the pull-down transistor. The pull-up transistor has a bulk electrode connected to a switchable bulk line; an auxiliary circuit is provided which as long as a voltage of the output node is not higher than said supply voltage keeps said switchable bulk line connected to the voltage supply. The first logic gate includes circuitry for transferring the voltage of the output node to said switchable bulk line when the voltage of the output node exceeds the supply voltage.

REFERENCES:
patent: 5160855 (1992-11-01), Dobberpuhl
patent: 5300832 (1994-04-01), Rogers
patent: 5448198 (1995-09-01), Toyoshima et al.
patent: 5534795 (1996-07-01), Wert et al.
patent: 5539335 (1996-07-01), Kobayashi et al.
patent: 5546020 (1996-08-01), Lee et al.
patent: 5552723 (1996-09-01), Shigehara et al.
patent: 5646550 (1997-07-01), Campbell, Jr. et al.

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