Excavating
Patent
1993-01-08
1994-12-13
Beausoliel, Jr., Robert W.
Excavating
371 295, G06F 1100, H03M 1300
Patent
active
053735145
ABSTRACT:
A structure and method, useful in a test pattern generation system, for evaluating control and data input signals to a three state bus to determine whether the control input signals result in either a contention on the three state bus or floating of the three state bus is disclosed. Two parallel logic networks are used. A first logic network receives both the control input signals and data input signals and in turn generates an output signal that is the output signal of the three state bus. The second logic network receives only the control input signals and in turn generates an output signal having a first predetermined value when the bus output signal is valid and a second predetermined value when either a contention exists on the three state bus or the three state bus is floating. Selection of test vectors that produce only control signals that in turn produce an output signal from the second logic network having the first predetermined value results in selection of only valid test vectors.
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patent: 4225959 (1980-09-01), Suelflow et al.
patent: 4945540 (1990-07-01), Kaneko
patent: 5067132 (1991-11-01), Blakkan
Beausoliel, Jr. Robert W.
Hua Ly V.
Synopsys Inc.
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