Three stage power conditioning circuit

Electric power conversion systems – Current conversion – With means to introduce or eliminate frequency components

Reexamination Certificate

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Details

C307S105000

Reexamination Certificate

active

06288917

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to power conditioning circuits, and more particularly, to power conditioning circuits that protect attached load equipment from voltage and current surges due to, for example, lightning strikes or other power disturbances.
BACKGROUND ART
Power conditioning circuits have long been used to protect sensitive load equipment from transients caused by lightning strikes, noise and other power line disturbances. Traditionally, filter elements are used in the line and neutral conductors which trap and/or shunt unwanted power frequencies away from the load. See, for example, Speet et al. U.S. Pat. No. 4,814,941 and Taylor et al. U.S. Pat. No. 5,490,030.
Muelleman U.S. Pat. No. 5,448,443 discloses a power conditioning device and method including an isolation transformer having primary and secondary sides and a ground impedance connected between the secondary side of the isolation transformer at a safety ground and an earth ground. The Muelleman device prevents ground current loops by redirecting transient ground currents to neutral, but does not provide current limiting or noise suppression.
SUMMARY OF THE INVENTION
A power conditioning circuit is simple in design, yet effective to limit damaging transients.
More particularly, according to one aspect of the present invention, a power conditioning circuit for conditioning power supplied by a power source at a nominal frequency over line, neutral and ground conductors to first, second and third output lines, respectively, includes a first, second and third stage. The first stage is connected to the line, neutral and ground conductors, and is adapted to provide voltage suppression. The second stage is connected to the first stage, and includes first, second and third inductors coupled in series between the line, neutral and ground conductors, respectively, and the first, second and third output lines, respectively, and all of the power supplied by the power source to the first, second and third output lines flows through the first, second and third inductors. Each of the inductors block power at frequencies greater than the nominal frequency thereby to prevent power at frequencies greater than the nominal frequency from reaching the first, second and third output lines. The third stage is connected to the second stage and is further connected to the first, second and third output lines and is adapted to provide voltage suppression and voltage clamping.
According to another aspect of the present invention, the first stage includes first, second and third metal oxide varistors. The first metal oxide varistor is coupled between the line conductor and the neutral conductor and the second metal oxide varistor is coupled between the line conductor and the ground conductor and the third metal oxide varistor is coupled between the neutral conductor and the ground conductor.
Preferably, the first stage includes a capacitor coupled between the neutral conductor and the ground conductor.
According to yet another aspect of the present invention, the third stage includes a first metal oxide varistor, wherein the first metal oxide varistor is coupled between the neutral conductor and the ground conductor. The third stage may further include a second metal oxide varistor, wherein the second metal oxide varistor is coupled between the line conductor and the neutral conductor.
In addition to the foregoing, and according to a still further aspect of the present invention, the third stage includes first and second diodes coupled in anti-parallel relationship across the neutral conductor and the ground conductor. The third stage may further include a capacitor coupled between the neutral conductor and the ground conductor.
According to yet another aspect of the present invention, the first, second and third inductors are common mode inductors each having a core and a set of first and second windings. The first inductor is coupled between the line conductor and the first output line via the first winding of the first inductor and the first inductor is further coupled between the neutral conductor and the second output line via the second winding of the first inductor and the first and second windings of the first inductor are wound around the core of the first inductor. The second inductor is coupled between the neutral conductor and the second output line via the first winding of the second inductor and the second inductor is further coupled between the ground conductor and the third output line via the second winding of the second inductor and the first and second windings of the second inductor are wound around the core of the second inductor. The third inductor is coupled between the ground conductor and the third output line via the first winding of the third inductor and the third inductor is further coupled between the line conductor and the first output line via the second winding of the third inductor and the first and second windings of the third inductor are wound around the core of the third inductor. The first, second and third output lines of the power conditioning circuit of the present invention may be coupled to a load having a capacitive impedance and the first, second and third inductors may be rated to compensate for the capacitive impedance of the load.
Other aspects and advantages of the present invention will become apparent upon consideration of the following drawings and detailed description.


REFERENCES:
patent: 4429338 (1984-01-01), Becker et al.
patent: 4703386 (1987-10-01), Speet et al.
patent: 4802055 (1989-01-01), Beckerman
patent: 4814941 (1989-03-01), Speet et al.
patent: 4868732 (1989-09-01), Gillett et al.
patent: 4901183 (1990-02-01), Lee
patent: 4999729 (1991-03-01), Stifter
patent: 5105327 (1992-04-01), Wohlforth
patent: 5162963 (1992-11-01), Washburn et al.
patent: 5287288 (1994-02-01), Brennen et al.
patent: 5355025 (1994-10-01), Moran et al.
patent: 5448443 (1995-09-01), Muelleman
patent: 5465203 (1995-11-01), Bhattacharya et al.
patent: 5490030 (1996-02-01), Taylor et al.
patent: 5589718 (1996-12-01), Lee
patent: 5617284 (1997-04-01), Paradise
patent: 5731965 (1998-03-01), Cheng et al.
patent: 5757099 (1998-05-01), Cheng et al.
patent: 6166458 (2000-12-01), Redburn et al.
patent: WO 96/39735 (1996-12-01), None
patent: WO 99/37007 (1999-07-01), None

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