Three-stage binary coincidence detector apparatus with adaptive

Details Three-stage binary coincidence detector apparatus with adaptive Three-stage binary coincidence detector apparatus with adaptive

1982-05-26

1985-06-11

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Counter controlled counter

343 5CF, 328115, 328119, 307362, H03K 1300

Patent

active

045233250

ABSTRACT:
A target processor utilizing a feedback loop to maintain a constant false alarm rate for variable level video input signals with noise or noise plus clutter on the input signal. The processor includes three serially connected stages of binary coincidence detectors which comprise a threshold detector for processing video signals which exceed a threshold level, an M of N detector for providing an alarm for each range gate having a count of M or greater pulses, and a P of Q detector for generating a target alarm after at least P or greater frequencies have been transmitted.

REFERENCES:
patent: 3797014 (1974-03-01), Tompkins et al.
patent: 3838422 (1974-09-01), McArthur et al.
patent: 4062012 (1977-12-01), Colbert et al.
patent: 4249177 (1981-02-01), Chen
Radar Detection in Weilbull Clutter by D. C. Schleher, IEEE Transactions on Aerospace & Elec. Systems, vol. AES 12, No. 6, Nov. 1976.
A Coincidence Procedure for Signal Detection by Mischa Schwartz, IRE Transactions on Information Theory Mar./Dec. 1956.

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