Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
2000-11-27
2002-09-10
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
C327S175000, C327S178000, C377S044000, C377S126000
Reexamination Certificate
active
06448827
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a pulse width modulation inverter for varying speed of an AC-motor, and more particularly to a three-phase pulse width modulation waveform generator to be used for an inverter which uses a high speed switching such as a compound semiconductor bipolar transistor.
A triangle pulse wave modulation method is one of methods for generating a pulse width modulation signal.
FIG. 1
is a diagram illustrative of waveforms of sign waves (U, V, W) and triangle wave for explaining a triangle pulse wave modulation method. The sign waves (U, V, W) are modulated with the triangle wave
401
.
The three-phase pulse width modulation waveform generator comprises a first pulse width modulation waveform generator circuit for generating +U-phase and −U-phase pulse width modulation waveforms, a second pulse width modulation waveform generator circuit for generating +V-phase and −V-phase pulse width modulation waveforms, and a third pulse width modulation waveform generator circuit for generating +W-phase and −W-phase pulse width modulation waveforms.
FIG. 2A
is a circuit diagram illustrative of a circuit configuration of a first pulse width modulation waveform generator circuit for generating +U-phase and −U-phase pulse width modulation waveforms in a conventional three-phase pulse width modulation waveform generator. The first pulse width modulation waveform generator circuit of the three-phase pulse width modulation waveform generator has the following circuit elements. An up-down counter
1
which receives a count clock
2
is provided for performing up-count and down-count. A count register
3
is connected to the up-down counter
1
for storing a switching value and sending the switching value to the up-down counter
1
so that the up-down counter
1
switches from the up-count to the down-count in accordance with the switching value. A first buffer register
4
is connected to the count register
3
. The first buffer register
4
receives a first transfer enabling signal
5
and transfer data to the counter resistor
3
in accordance with the first transfer enabling signal
5
. A comparator
6
is connected to the up-down counter
1
. A comparative register
7
is connected to the comparator
6
. The comparative register
7
stores data for generating a U-phase pulse width modulation signal. A second buffer register
8
receiving a second transfer enabling signal
9
is connected to the comparative register
7
for transferring stored data to the comparative register
7
in accordance with the second transfer enabling signal
9
. A delay circuit
10
is connected to the comparator
6
for generating a dead time which prevents formation of a short circuit. A waveform generator
14
is connected to the up-down counter
1
for receiving one of count direction signals
11
which indicate the up-count and the down-count from the up-down counter
1
. The waveform generator
14
is also connected to the comparator
6
for receiving a correspondence-detected signal
12
from the comparator
6
. The waveform generator
14
is also connected to the delay circuit
10
for receiving a delay signal from the delay circuit
10
. The waveform generator
14
generates an +U-phase pulse width modulation signal
15
and a −U-phase pulse width modulation signal
16
. A first three-state buffer
17
is provided which has an input terminal connected to the waveform generator
14
for receiving the +U-phase pulse width modulation signal
15
from the waveform generator
14
. The first three-state buffer
17
receives an output stop signal
19
, so that the first three-state buffer
17
stops the output of the +U-phase pulse width modulation signal
15
. A second three-state buffer
18
is provided which has an input terminal connected to the waveform generator
14
for receiving the −U-phase pulse width modulation signal
16
from the waveform generator
14
. The second three-state buffer
18
receives the output stop signal
19
, so that the second three-state buffer
18
stops the output of the −U-phase pulse width modulation signal
16
.
FIG. 2B
is a circuit diagram illustrative of a circuit configuration of a second pulse width modulation waveform generator circuit for generating +V-phase and −V-phase pulse width modulation waveforms in the conventional three-phase pulse width modulation waveform generator. The second pulse width modulation waveform generator circuit of the three-phase pulse width modulation waveform generator has the same circuit elements as the first pulse width modulation waveform generator circuit. Namely, an up-down counter
1
which receives a count clock
2
is provided for performing up-count and down-count. A count register
3
is connected to the up-down counter
1
for storing a switching value and sending the switching value to the up-down counter
1
so that the up-down counter
1
switches from the up-count to the down-count in accordance with the switching value. A first buffer register
4
is connected to the count register
3
. The first buffer register
4
receives a first transfer enabling signal
5
and transfer data to the counter resistor
3
in accordance with the first transfer enabling signal
5
. A comparator
6
is connected to the up-down counter
1
. A comparative register
7
is connected to the comparator
6
. The comparative register
7
stores data for generating a V-phase pulse width modulation signal. A second buffer register
8
receiving a second transfer enabling signal
9
is connected to the comparative register
7
for transferring stored data to the comparative register
7
in accordance with the second transfer enabling signal
9
. A delay circuit
10
is connected to the comparator
6
for generating a dead time which prevents formation of a short circuit. A waveform generator
14
is connected to the up-down counter
1
for receiving one of count direction signals
11
which indicate the up-count and the down-count from the up-down counter
1
. The waveform generator
14
is also connected to the comparator
6
for receiving a correspondence-detected signal
12
from the comparator
6
. The waveform generator
14
is also connected to the delay circuit
10
for receiving a delay signal from the delay circuit
10
. The waveform generator
14
generates an +V-phase pulse width modulation signal
15
and a −V-phase pulse width modulation signal
16
. A first three-state buffer
17
is provided which has an input terminal connected to the waveform generator
14
for receiving the +V-phase pulse width modulation signal
15
from the waveform generator
14
. The first three-state buffer
17
receives an output stop signal
19
, so that the first three-state buffer
17
stops the output of the +V-phase pulse width modulation signal
15
. A second three-state buffer
18
is provided which has an input terminal connected to the waveform generator
14
for receiving the −V-phase pulse width modulation signal
16
from the waveform generator
14
. The second three-state buffer
18
receives the output stop signal
19
, so that the second three-state buffer
18
stops the output of the −V-phase pulse width modulation signal
16
.
FIG. 2C
is a circuit diagram illustrative of a circuit configuration of a third pulse width modulation waveform generator circuit for generating +W-phase and −W-phase pulse width modulation waveforms in the conventional three-phase pulse width modulation waveform generator. The third pulse width modulation waveform generator circuit of the three-phase pulse width modulation waveform generator has the same circuit elements as the first pulse width modulation waveform generator circuit. Namely, an up-down counter
1
which receives a count clock
2
is provided for performing up-count and down-count. A count register
3
is connected to the up-down counter
1
for storing a switching value and sending the switching value to the up-down counter
Callahan Timothy P.
Luu An T.
NEC Corporation
Young & Thompson
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