Three phase line-addressable serial-parallel-serial storage arra

Details Three phase line-addressable serial-parallel-serial storage arra Three phase line-addressable serial-parallel-serial storage arra

1978-12-29

1980-09-30

Fears, Terrell W.

Static information storage and retrieval

Addressing

Byte or page addressing

365 45, 365183, 365189, 307238, G11C 1140, G11C 1300

Patent

active

042259479

ABSTRACT:
Disclosed is an electronic data storage of the type wherein data is entered and read out serially. In a conventional serial-parallel-serial configuration, data is serially entered into an input register and then transferred and stored in parallel through the main section of the storage until data is transferred in parallel to the output register from which the data is read serially. In a conventional line-addressable configuration, data is entered into and read from columns of shift registers where each column is addressable. The disclosed array combines the conventional serial-parallel-serial and the line-addressable structures into one array. By utilizing three phase clock lines and an inhibit line for each cell, the disclosed structure can be fabricated with two levels of gate electrodes.

REFERENCES:
patent: 3763480 (1973-10-01), Weimer
patent: 3914748 (1975-10-01), Barton et al.
patent: 3953837 (1976-04-01), Cheek, Jr.
patent: 4011548 (1977-03-01), Panigrahi
patent: 4024512 (1977-05-01), Amelio et al.
patent: 4092734 (1978-05-01), Collins et al.
patent: 4094009 (1978-06-01), Schneider et al.
patent: 4152780 (1979-05-01), Eberlin

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