Three phase charge-coupled device memory with inhibit lines

Details Three phase charge-coupled device memory with inhibit lines Three phase charge-coupled device memory with inhibit lines

1975-07-02

1977-03-08

Curtis, Marshall M.

Communications: electrical

Digital comparator systems

340173PP, 357 24, G11C 1144

Patent

active

040115488

ABSTRACT:
A charge coupled device shift register memory structure wherein the shift registers may be selectively activated. Each shift register is clocked by a common set of clock phase electrodes. Individual inhibit lines are placed over each shift register channel, and by applying appropriate voltages to these inhibit lines shifting of data in the underlying channel is prevented. In one embodiment, a channel decoder, common source and drain lines and cooperating gating circuitry facilitate read/write and refresh operations.

REFERENCES:
patent: 3792322 (1974-02-01), Boyle et al.
patent: 3858232 (1974-12-01), Boyle et al.
patent: 3890633 (1975-06-01), Kosonocky
patent: 3918997 (1975-11-01), Mohsen et al.

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