Three-path fused multiply-adder circuit

Details Three-path fused multiply-adder circuit Three-path fused multiply-adder circuit

2008-04-09

2011-10-11

Malzahn, David H (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

08037118

ABSTRACT:
A three-path floating-point fused multiply-adder is disclosed. The fused multiply-adder is for the single instruction execution of (A×B)+C. The three-path fused multiply-adder is based on a dual-path adder and reduces latency significantly by operating on case data in parallel and by reducing component bit size. The fused multiply-adder is a common serial fused multiply-adder that reuses floating-point adder (FPA) and floating-point multiplier (FPM) hardware, allowing single adds, single multiplies, and fused multiply-adds to execute at maximum speed.

REFERENCES:
patent: 7461117 (2008-12-01), Trong et al.
patent: 7840622 (2010-11-01), Gerwig et al.
patent: 2008/0256161 (2008-10-01), Quinnell et al.
patent: 2008/0256162 (2008-10-01), Henry et al.
patent: 2009/0077152 (2009-03-01), Powell et al.
patent: 2009/0248779 (2009-10-01), Brooks et al.
patent: 2011/0040815 (2011-02-01), Penton et al.

Affiliated with

Also associated with

Rating

Three-path fused multiply-adder circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Three-path fused multiply-adder circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Three-path fused multiply-adder circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4256150