Three output level logic circuit

Details Three output level logic circuit Three output level logic circuit

1977-04-25

1979-05-01

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307217, 307243, 328 99, H03K 1908

Patent

active

RE0299820

ABSTRACT:
A three-output level logic circuit in which in addition to zero and one binary logic levels a third off-logic level is provided in which the output impedance is relatively high to in effect isolate the switching circuit from a common line to which it is connected thereby allowing several switching circuits to be used in common without deleteriously affecting switching speed in an overall computer or calculator unit.

REFERENCES:
patent: 3207922 (1965-09-01), Gruodis
patent: 3212009 (1965-10-01), Parker
patent: 3333113 (1967-07-01), Cole
patent: 3381088 (1968-04-01), Lentz et al.
patent: 3431433 (1969-03-01), Ball et al.
patent: 3467948 (1969-09-01), Barlow et al.
patent: 3492496 (1970-01-01), Callan
IBM Technical Disclosure Bulletin, J. B. Atkins, "Inhibited Logic Circuit" vol. 7, No. 9, Feb., 1965, p. 848.
Electronic Design, Jun. 6, 1968, p. 85.
R. G. Short, "MOS FET Shift Register Element" IBM Technical Disclosure Bulletin, vol. 9, No. 8, Jan., 1967, pp. 1047-1049.

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