Three mask self aligned IGFET fabrication process

Details Three mask self aligned IGFET fabrication process Three mask self aligned IGFET fabrication process

1975-04-29

1976-05-25

Tupman, W.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 357 59, B01J 1700

Patent

active

039583236

ABSTRACT:
A process is disclosed for making a self-aligned IGFET having a polycrystalline silicon gate, using three masking steps. Layers of silicon dioxide, polycrystalline silicon, and silicon nitride are respectively deposited on the surface of a silicon substrate of a first conductivity type. With the first mask, openings are made in regions of these layers above the proposed location for the source and drain. The source and drain are then deposited in the substrate through these openings. The disclosed process continues, growing a silicon dioxide layer on the lateral surfaces of the polysilicon gate, exposed by these openings. Then a silicon nitride layer is deposited on all exposed surfaces and a second mask is employed to permit the removal by etching of this nitride layer from all portions except the proposed location of devices metallization at a first region over the gate, a second region over the source and a third region over the drain of the device. The polycrystalline silicon layer is then etched and removed from the field region of the device. Polysilicon material in the gate region is protected during this etching stop by the first nitride layer and the silicon dioxide layer grown over the lateral exposed surfaces of the gate. The nitride layer regions are then etched away and metallized contacts are formed to the source, drain and polycrystalline silicon gate regions by means of a third and last mask. Alternative steps are disclosed for making the gate and field oxide regions coplanar.

REFERENCES:
patent: 3673471 (1972-06-01), Klein
patent: 3711753 (1973-01-01), Brand
patent: 3761327 (1973-09-01), Harlow
patent: 3837071 (1974-09-01), Ronen
patent: 3913211 (1975-10-01), Seeds

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